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Interrupt request
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<h2 id="overview">Overview</h2> <p>When working with personal computer hardware, installing and removing devices, the system relies on interrupt requests. There are default settings that are configured in the system <a href="/facts/BIOS/AYYPUogS">BIOS</a> and recognized by the operating system. These default settings can be altered by advanced users. Modern <a href="/facts/Plug_and_play/LISny9tL">plug and play</a> technology has not only reduced the need for concern for these settings, but has also virtually eliminated manual configuration. </p> <h2 id="x86-irqs">x86 IRQs</h2> <p>Early PCs using the Intel 8086/8088 processors only had a single PIC, and are therefore limited to eight interrupts. This was expanded to two PICs with the introduction of the 286 based PCs. </p><p>Typically, on systems using the <a href="/facts/Intel_8259/Y5FhqM6G">Intel 8259</a> PIC, 16 IRQs are used. IRQs 0 to 7 are managed by one Intel 8259 PIC, and IRQs 8 to 15 by a second Intel 8259 PIC. The first PIC, the master, is the only one that directly signals the CPU. The second PIC, the slave, instead signals to the master on its IRQ 2 line, and the master passes the signal on to the CPU. There are therefore only 15 interrupt request lines available for hardware. </p><p>On APIC with <a href="/facts/IOAPIC/40lXS8r6">IOAPIC</a> systems, typically there are 24 IRQs available, and the extra 8 IRQs are used to route PCI interrupts, avoiding conflict between dynamically configured PCI interrupts and statically configured ISA interrupts. On early APIC systems with only 16 IRQs or with only Intel 8259 interrupt controllers, PCI interrupt lines were routed to the 16 IRQs using a PIR (PCI interrupt routing) table integrated into the BIOS. Operating systems such as <a href="/facts/Windows_95_OSR2/1E1L93qC">Windows 95 OSR2</a> may use PIR table to process PCI IRQ steering;<a class="footnote-ref" id="fnref:3" href="#fn:3"><sup>3</sup></a><a class="footnote-ref" id="fnref:4" href="#fn:4"><sup>4</sup></a> later, the PIR table has been superseded by the <a href="/facts/ACPI/odRvjcxt">ACPI</a> _PRT (PCI routing table) protocol. On APIC with <a href="/facts/Message_Signaled_Interrupts/4Qoe88JY">MSI</a> systems, typically there are 224 interrupts available.<a class="footnote-ref" id="fnref:5" href="#fn:5"><sup>5</sup></a> </p><p>The easiest way of viewing this information on <a href="/facts/Microsoft_Windows/bwhAhuSL">Windows</a> is to use <a href="/facts/Device_Manager/zECWES62">Device Manager</a> or <a href="/facts/System_Information_(Windows)/M6NVNa7S">System Information</a> (msinfo32.exe). On <a href="/facts/Linux/9FvCKSTq">Linux</a>, IRQ mappings can be viewed by executing cat /proc/interrupts or using the procinfo utility. </p> <h3>Master PIC</h3> <ul><li>IRQ 0 – <a href="/facts/Programmable_interval_timer/2hpRmVAl">system timer</a> (cannot be changed)</li> <li>IRQ 1 – <a href="/facts/Computer_keyboard/MczF9LIS">keyboard</a> on <a href="/facts/PS%2f2_port/43gxjWdS">PS/2 port</a> (cannot be changed)</li> <li>IRQ 2 – <a href="/facts/8259/Y5FhqM6G">8259</a> interrupt controller; cascaded signals from IRQs 8–15</li> <li>IRQ 3 – <a href="/facts/Serial_port/VpcrH530">serial port</a> <a href="/facts/Universal_asynchronous_receiver%2ftransmitter/xMntJcsI">controller</a> for <a href="/facts/COM_(hardware_interface)/0sMVyT0H">serial port</a> 2 (shared with serial port 4, if present)</li> <li>IRQ 4 – serial port controller for serial port 1 (shared with serial port 3, if present)</li> <li>IRQ 5 – <a href="/facts/Parallel_port/qpkjH8ts">parallel port</a> 3 or <a href="/facts/Sound_card/bxlF4YBa">ISA sound card</a></li> <li>IRQ 6 – <a href="/facts/Floppy_disk_controller/re4fpWCW">floppy disk controller</a></li> <li>IRQ 7 – parallel port 1 (shared with parallel port 2, if present). It can also be potentially be shared with a secondary ISA sound card with careful management of the port.</li></ul> <h3>Slave PIC</h3> <ul><li>IRQ 8 – <a href="/facts/Real-time_clock/pYeXraUW">real-time clock</a> (RTC)</li> <li>IRQ 9 – <a href="/facts/Advanced_Configuration_and_Power_Interface/GnLLzfyr">Advanced Configuration and Power Interface</a> (ACPI) system control interrupt on Intel chipsets.<a class="footnote-ref" id="fnref:6" href="#fn:6"><sup>6</sup></a> And/or left for the use of peripherals (use depends on OS)</li> <li>IRQ 10 – The interrupt is left for the use of peripherals (for example, <a href="/facts/SCSI/pxXulrBr">SCSI</a> or <a href="/facts/Network_card/wyf5FR29">NIC</a>)</li> <li>IRQ 11 – The interrupt is left for the use of peripherals (for example, SCSI or NIC)</li> <li>IRQ 12 – <a href="/facts/Computer_mouse/fJpa1tUE">mouse</a> on <a href="/facts/PS%2f2_port/43gxjWdS">PS/2 port</a></li> <li>IRQ 13 – CPU <a href="/facts/Co-processor/WsVXzAGo">co-processor</a> or integrated <a href="/facts/Floating_point_unit/XWTW2AbF">floating point unit</a> or <a href="/facts/Inter-processor_interrupt/dddXBU0I">inter-processor interrupt</a> (use depends on OS)</li> <li>IRQ 14 – primary <a href="/facts/Parallel_ATA/QPchqXH8">ATA</a> channel (ATA interface usually serves <a href="/facts/Hard_disk_drive/kekLSGSE">hard disk drives</a> and <a href="/facts/CD_drive/IM9ugGbU">CD drives</a>)</li> <li>IRQ 15 – secondary ATA channel</li></ul> <h2 id="conflicts">Conflicts</h2> <p>In early IBM-compatible <a href="/facts/Personal_computer/koaYfNce">personal computers</a>, an <i>IRQ conflict</i> is a once common hardware error, received when two devices were trying to use the same interrupt request (or IRQ) to signal an interrupt to the <a href="/facts/Programmable_Interrupt_Controller/0ukSAuF1">Programmable Interrupt Controller</a> (PIC). The PIC expects interrupt requests from only one device per line, thus more than one device sending IRQ signals along the same line will generally cause an IRQ conflict that can freeze a <a href="/facts/Computer/SQe1aK05">computer</a>. </p><p>For example, if a <a href="/facts/Modem/9H0Xwtq0">modem</a> <a href="/facts/Expansion_card/QkWAPnxJ">expansion card</a> is added into a system and assigned to IRQ4, which is traditionally assigned to the <a href="/facts/COM_(hardware_interface)/0sMVyT0H">serial port</a> 1, it will likely cause an IRQ conflict. Initially, IRQ 7 was a common choice for the use of a <a href="/facts/Sound_card/bxlF4YBa">sound card</a>, but later IRQ 5 was used when it was found that IRQ 7 would interfere with the <a href="/facts/Printer_port/qpkjH8ts">printer port</a> (<a href="/facts/DOS/sWwDXNmX">LPT1</a>). The <a href="/facts/Serial_port/VpcrH530">serial ports</a> are frequently disabled to free an IRQ line for another device. IRQ 2/9 is the traditional interrupt line for an MPU-401 MIDI port, but this conflicts with the <a href="/facts/Advanced_Configuration_and_Power_Interface/GnLLzfyr">ACPI</a> system control interrupt (SCI is hardwired to IRQ9 on Intel chipsets);<a class="footnote-ref" id="fnref:7" href="#fn:7"><sup>7</sup></a> this means ISA <a href="/facts/MPU-401/PnjVQbLX">MPU-401</a> cards with a hardwired IRQ 2/9, and MPU-401 device drivers with a hardcoded IRQ 2/9, cannot be used in interrupt-driven mode on a system with ACPI enabled. </p><p>In some conditions, two <a href="/facts/ISA_bus/5Rk4bjqB">ISA</a> devices could share the same IRQ as long as they were not used simultaneously. To solve this problem, the later <a href="/facts/PCI_bus/n6CGuFvP">PCI bus</a> allows for IRQ sharing. <a href="/facts/PCI_Express/ADhsLCUK">PCI Express</a> does not have physical interrupt lines, and uses <a href="/facts/Message_Signaled_Interrupts/4Qoe88JY">Message Signaled Interrupts</a> (MSI) to the <a href="/facts/Operating_system/8XTuvMh2">operating systems</a> if available. </p> <h2 id="see-also">See also</h2> <ul><li><a href="/facts/Advanced_Programmable_Interrupt_Controller/40lXS8r6">Advanced Programmable Interrupt Controller</a> (APIC)</li> <li><a href="/facts/Programmable_Interrupt_Controller/0ukSAuF1">Programmable Interrupt Controller</a> (PIC)</li> <li><a href="/facts/Intel_8259/Y5FhqM6G">Intel 8259</a></li> <li><a href="/facts/Interrupt_handler/r9ptAjy7">Interrupt handler</a></li> <li><a href="/facts/Plug_and_play/LISny9tL">Plug and play</a></li> <li><a href="/facts/Polling_(computer_science)/WVa88JIg">Polling</a></li> <li><a href="/facts/Interrupt/Mm6C4rpc">Interrupt</a></li></ul> <h2 id="further-reading">Further reading</h2> <ul><li>Gilluwe, Frank van. <i>The Undocumented PC, Second Edition</i>, Addison-Wesley Developers Press, 1997. <a href="/facts/ISBN_(identifier)/15AdSPa9">ISBN</a> 0-201-47950-8</li> <li>Shanley, Tom; Anderson, Don (1995). Swindle, John (ed.). <a href="https://archive.org/details/ISA_System_Architecture"><i>ISA System Architecture</i></a> (3 ed.). Mindshare, Inc. / <a href="/facts/Addison-Wesley_Publishing_Company/A7UFATEG">Addison-Wesley Publishing Company</a>. <a href="/facts/ISBN_(identifier)/15AdSPa9">ISBN</a> 0-201-40996-8. <a href="/facts/ISBN_(identifier)/15AdSPa9">ISBN</a> 978-0-201-40996-3. <a href="https://books.google.com/books?id=-pz8rvnhFDkC">[1]</a></li> <li>Solari, Edward. <i>PCI & PCI-X Hardware and Software Architecture & Design, Sixth Edition</i>, Research Tech Inc., 2004. <a href="/facts/ISBN_(identifier)/15AdSPa9">ISBN</a> 0-9760865-0-6</li></ul> <h2 id="external-links">External links</h2> <ul><li><a href="https://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-software-developer-vol-3a-part-1-manual.html">Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A: System Programming Guide, Part 1, chapter 6</a> – more information on Intel 64 and IA-32 interrupt handling</li> <li><a href="https://www.cs.cmu.edu/~ralf/files.html">Ralf Brown's Interrupt List</a></li></ul> <h2 id="references">References</h2> <ol> <li id="fn:1"><p>"IOAPIC - OSDev Wiki". wiki.osdev.org. Retrieved 2024-11-07. <a href="https://wiki.osdev.org/IOAPIC" target="_blank">https://wiki.osdev.org/IOAPIC</a> <a href="#fnref:1" class="footnote-back-ref">↩</a></p></li> <li id="fn:2"><p>"IRQ". Retrieved September 13, 2019. <a href="https://www.computerhope.com/jargon/i/irq.htm" target="_blank">https://www.computerhope.com/jargon/i/irq.htm</a> <a href="#fnref:2" class="footnote-back-ref">↩</a></p></li> <li id="fn:3"><p>"1.3.1.2. PCI Bus IRQ Steering - PC Hardware in a Nutshell, 3rd Edition [Book]". <a href="https://www.oreilly.com/library/view/pc-hardware-in/059600513X/ch01s03s01s02.html" target="_blank">https://www.oreilly.com/library/view/pc-hardware-in/059600513X/ch01s03s01s02.html</a> <a href="#fnref:3" class="footnote-back-ref">↩</a></p></li> <li id="fn:4"><p>"Plug-and-Play-HOWTO: PCI Interrupts". <a href="https://tldp.org/HOWTO/Plug-and-Play-HOWTO-7.html" target="_blank">https://tldp.org/HOWTO/Plug-and-Play-HOWTO-7.html</a> <a href="#fnref:4" class="footnote-back-ref">↩</a></p></li> <li id="fn:5"><p>Coleman, James (2009). "Results, Workstation Class Platform". Reducing Interrupt Latency Through the Use of Message Signalled Interrupts (PDF). Intel Corporation. p. 19. <a href="https://www.intel.com/content/dam/www/public/us/en/documents/white-papers/msg-signaled-interrupts-paper.pdf" target="_blank">https://www.intel.com/content/dam/www/public/us/en/documents/white-papers/msg-signaled-interrupts-paper.pdf</a> <a href="#fnref:5" class="footnote-back-ref">↩</a></p></li> <li id="fn:6"><p>Oshins, Jake (December 30, 2001). "RE: ACPI Machines and IRQ 9 [was: Communicating with the NT developers]". Retrieved April 17, 2014. <a href="http://www.osronline.com/showThread.cfm?link=21604" target="_blank">http://www.osronline.com/showThread.cfm?link=21604</a> <a href="#fnref:6" class="footnote-back-ref">↩</a></p></li> <li id="fn:7"><p>Oshins, Jake (December 30, 2001). "RE: ACPI Machines and IRQ 9 [was: Communicating with the NT developers]". Retrieved April 17, 2014. <a href="http://www.osronline.com/showThread.cfm?link=21604" target="_blank">http://www.osronline.com/showThread.cfm?link=21604</a> <a href="#fnref:7" class="footnote-back-ref">↩</a></p></li> </ol>