Multi-level cell

<h2 id="single-level-cell">Single-level cell</h2>
<a href="/facts/Flash_memory/Cn8JsStx">Flash memory</a> stores data in individual memory cells, which are made of <a href="/facts/Floating-gate_MOSFET/AvmK0oBb">floating-gate MOSFET</a> transistors. Traditionally, each cell had two possible states (each with one voltage level), with each state representing either a one or a zero, so one <a href="/facts/Bit/S972NSaD">bit</a> of data was stored in each cell in so-called single-level cells, or SLC flash memory. SLC memory has the advantage of higher write speeds, lower power consumption and higher cell endurance. However, because SLC memory stores less data per cell than MLC memory, it costs more per megabyte of storage to manufacture. Due to higher transfer speeds and expected longer life, SLC flash technology is used in high-performance <a href="/facts/Memory_card/Rwy2lKS2">memory cards</a>.
In February 2016, a study was published that showed little difference in practice between the reliability of SLC and MLC.<a class="footnote-ref" id="fnref:3" href="#fn:3">3</a>
A single-level cell (SLC) flash memory may have a lifetime of about 50,000 to 100,000 program/erase cycles.<a class="footnote-ref" id="fnref:4" href="#fn:4">4</a>
A single-level cell represents a 1 when almost empty and a 0 when almost full. There is a region of uncertainty (a read margin) between the two possible states at which the data stored in the cell cannot be precisely read.<a class="footnote-ref" id="fnref:5" href="#fn:5">5</a>

<h2 id="multi-level-cell">Multi-level cell</h2>
The primary benefit of MLC flash memory is its lower cost per unit of storage due to the higher data density, and memory-reading software can compensate for a larger <a href="/facts/Bit_error_rate/ovAAPFjV">bit error rate</a>.<a class="footnote-ref" id="fnref:6" href="#fn:6">6</a> The higher error rate necessitates an <a href="/facts/Error-correcting_code/cLUTUJrA">error-correcting code</a> (ECC) that can correct multiple bit errors; for example, the <a href="/facts/SandForce/YcqMaR3p">SandForce</a> SF-2500 flash controller can correct up to 55 bits per 512-byte sector with an unrecoverable read error rate of less than one sector per 1017 bits read.<a class="footnote-ref" id="fnref:7" href="#fn:7">7</a> The most commonly used algorithm is Bose–Chaudhuri–Hocquenghem (<a href="/facts/BCH_code/1KelJGxF">BCH code</a>).<a class="footnote-ref" id="fnref:8" href="#fn:8">8</a> Other drawbacks of MLC NAND are lower write speeds, lower number of program/erase cycles and higher power consumption compared to SLC flash memory.
Read speeds can also be lower for MLC NAND than SLC due to the need to read the same data at a second threshold voltage to help resolve errors. TLC and QLC devices may need to read the same data up to 4 and 8 times respectively to obtain values that are correctable by ECC.<a class="footnote-ref" id="fnref:9" href="#fn:9">9</a>
MLC flash may have a lifetime of about 1,000 to 10,000 program/erase cycles. This typically necessitates the use of a <a href="/facts/Flash_file_system/WX2fXBHU">flash file system</a>, which is designed around the limitations of flash memory, such as using <a href="/facts/Wear_leveling/N6ot7lGA">wear leveling</a> to extend the useful lifetime of the flash device.
The <a href="/facts/Intel_8087/YGDyGKAS">Intel 8087</a> used two-bits-per-cell technology for its <a href="/facts/Microcode/XQEsr2X3">microcode</a> <a href="/facts/ROM/P9QMuDLH">ROM</a>,<a class="footnote-ref" id="fnref:10" href="#fn:10">10</a> and in 1980 was one of the first devices on the market to use multi-level ROM cells.<a class="footnote-ref" id="fnref:11" href="#fn:11">11</a><a class="footnote-ref" id="fnref:12" href="#fn:12">12</a> <a href="/facts/Intel/SMF0gJJX">Intel</a> later demonstrated 2-bit multi-level cell (MLC) <a href="/facts/NOR_flash/Cn8JsStx">NOR flash</a> in 1997.<a class="footnote-ref" id="fnref:13" href="#fn:13">13</a> <a href="/facts/NEC/YnlUsMBA">NEC</a> demonstrated quad-level cells in 1996, with a 64 <a href="/facts/Mebibit/sbVr3xfY">Mbit</a> <a href="/facts/Flash_memory/Cn8JsStx">flash memory</a> chip storing 2 bits per cell. In 1997, NEC demonstrated a <a href="/facts/Dynamic_random-access_memory/koI9FGo5">dynamic random-access memory</a> (DRAM) chip with quad-level cells, holding a capacity of 4 Gbit. <a href="/facts/STMicroelectronics/4gbGJTVr">STMicroelectronics</a> also demonstrated quad-level cells in 2000, with a 64 Mbit <a href="/facts/NOR_flash/Cn8JsStx">NOR flash</a> memory chip.<a class="footnote-ref" id="fnref:14" href="#fn:14">14</a> 
MLC is used to refer to cells that store 2 bits per cell, using 4 charge values or levels. A 2-bit MLC has a single charge level assigned to every possible combination of ones and zeros, as follows: When close to 25% full, the cell represents a binary value of 11; when close to 50%, the cell represents a 01; when close to 75%, the cell represents a 00; and when close to 100%, the cell represents a 10. Once again, there is a region of uncertainty (read margin) between values, at which the data stored in the cell cannot be precisely read.<a class="footnote-ref" id="fnref:15" href="#fn:15">15</a><a class="footnote-ref" id="fnref:16" href="#fn:16">16</a>
As of 2013, some <a href="/facts/Solid-state_drives/aMHBy8gU">solid-state drives</a> use part of an MLC NAND die as if it were single-bit SLC NAND, giving higher write speeds.<a class="footnote-ref" id="fnref:17" href="#fn:17">17</a><a class="footnote-ref" id="fnref:18" href="#fn:18">18</a><a class="footnote-ref" id="fnref:19" href="#fn:19">19</a> 
As of 2018, nearly all commercial MLCs are planar-based (i.e. cells are built on silicon surface) and so subject to scaling limitations. To address this potential problem, the industry is already looking at technologies that can guarantee storage density increases beyond today’s limitations. One of the most promising is 3D Flash, where cells are stacked vertically, thereby avoiding the limitations of planar scaling.<a class="footnote-ref" id="fnref:20" href="#fn:20">20</a>
In the past, a few memory devices went the other direction and used two cells per bit to give even lower bit error rates.<a class="footnote-ref" id="fnref:21" href="#fn:21">21</a>
Enterprise MLC (eMLC) is a more expensive variant of MLC that is optimized for commercial use. It claims to last longer and be more reliable than normal MLCs while providing cost savings over traditional SLC drives. Although many SSD manufacturers have produced MLC drives intended for enterprise use, only Micron sells raw NAND Flash chips under this designation.<a class="footnote-ref" id="fnref:22" href="#fn:22">22</a>

<h2 id="triple-level-cell">Triple-level cell</h2>

A triple-level cell (TLC) is a type of <a href="/facts/NAND_flash/Cn8JsStx">NAND flash</a> memory that stores 3 bits of information per cell. <a href="/facts/Toshiba/QHRaw8Tr">Toshiba</a> introduced memory with triple-level cells in 2009.<a class="footnote-ref" id="fnref:23" href="#fn:23">23</a>
With current technology a maximum lifetime of up to 3,000 program/erase cycles is achievable.<a class="footnote-ref" id="fnref:24" href="#fn:24">24</a>
<a href="/facts/Samsung/oNXUwDjn">Samsung</a> announced a type of NAND flash that stores 3 bits of information per cell, with 8 total voltage states (values or levels), coining the term "triple-level cell" ("TLC"). <a href="/facts/Samsung_Electronics/STxnmHwl">Samsung Electronics</a> began mass-producing it in 2010,<a class="footnote-ref" id="fnref:25" href="#fn:25">25</a> and it was first seen in Samsung's 840 Series <a href="/facts/Solid-state_drive/aMHBy8gU">SSDs</a>.<a class="footnote-ref" id="fnref:26" href="#fn:26">26</a> Samsung refers to this technology as 3-bit MLC. The negative aspects of MLC are amplified with TLC, but TLC benefits from still higher storage density and lower cost.<a class="footnote-ref" id="fnref:27" href="#fn:27">27</a> 
In 2013, Samsung introduced <a href="/facts/V-NAND/Cn8JsStx">V-NAND</a> (Vertical NAND, also known as 3D NAND) with triple-level cells, which had a memory capacity of 128 <a href="/facts/Gibibit/cd5x20hM">Gbit</a>.<a class="footnote-ref" id="fnref:28" href="#fn:28">28</a> They expanded their TLC V-NAND technology to 256 Gbit memory in 2015,<a class="footnote-ref" id="fnref:29" href="#fn:29">29</a> and 512 Gbit in 2017.<a class="footnote-ref" id="fnref:30" href="#fn:30">30</a>
Enterprise TLC (eTLC) is a more expensive variant of TLC that is optimized for commercial use.

<h2 id="quad-level-cell">Quad-level cell</h2>

Memory that stores 4 bits per cell is commonly referred to as quad-level cell (QLC), following the convention set by TLC. Prior to its invention, the term "QLC" was synonymous with MLC in referring to cells that can have 4 voltage states, i.e. ones that store 2 bits per cell – what is now unambiguously referred to as DLC.
Due to the exponentially increasing number of required voltage stages for higher level flash the lifetime of QLC is further reduced to a maximum of 1,000 program/erase cycles.<a class="footnote-ref" id="fnref:31" href="#fn:31">31</a>
In 2009, Toshiba and <a href="/facts/SanDisk/ExLEXvQB">SanDisk</a> introduced <a href="/facts/NAND_flash/Cn8JsStx">NAND flash</a> memory chips with quad-level cells, storing 4 bits per cell and holding a capacity of 64 Gbit.<a class="footnote-ref" id="fnref:32" href="#fn:32">32</a><a class="footnote-ref" id="fnref:33" href="#fn:33">33</a>
SanDisk X4 flash memory cards, introduced in 2009, was one of the first products based on NAND memory that stores 4 bits per cell, commonly referred to as quad-level-cell (QLC), using 16 discrete charge levels (states) in each individual transistor. The QLC chips used in these memory cards were manufactured by Toshiba, SanDisk and <a href="/facts/SK_Hynix/U3yDU9JY">SK Hynix</a>.<a class="footnote-ref" id="fnref:34" href="#fn:34">34</a><a class="footnote-ref" id="fnref:35" href="#fn:35">35</a>
In 2017, Toshiba introduced V-NAND memory chips with quad-level cells, which have a storage capacity of up to 768 Gbit.<a class="footnote-ref" id="fnref:36" href="#fn:36">36</a> In 2018, <a href="/facts/ADATA/lxNfXI36">ADATA</a>, <a href="/facts/Intel/SMF0gJJX">Intel</a>, <a href="/facts/Micron_Technology/M5YhP13C">Micron</a> and Samsung have launched some SSD products using QLC NAND memory.<a class="footnote-ref" id="fnref:37" href="#fn:37">37</a><a class="footnote-ref" id="fnref:38" href="#fn:38">38</a><a class="footnote-ref" id="fnref:39" href="#fn:39">39</a><a class="footnote-ref" id="fnref:40" href="#fn:40">40</a>
In 2020, Samsung released a QLC SSD with storage space up to 8 TB for customers. It is the SATA SSD with the largest storage capacity for consumers as of 2020.<a class="footnote-ref" id="fnref:41" href="#fn:41">41</a><a class="footnote-ref" id="fnref:42" href="#fn:42">42</a>
Enterprise QLC (eQLC) is a more expensive variant of QLC that is optimized for commercial use.

<h2 id="see-also">See also</h2>
<ul><li><a href="/facts/StrataFlash/F5uJd6Yn">StrataFlash</a></li></ul>

<h2 id="external-links">External links</h2>
<ul><li><a href="http://www.linux-mtd.infradead.org/doc/nand.html">Linux Memory Technology Devices - NAND</a></li>
<li><a href="http://www.onfi.org">Open NAND Flash Interface</a></li></ul>

<h2 id="references">References</h2>

<ol>
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<li id="fn:32">"Toshiba Makes Major Advances in NAND Flash Memory with 3-bit-per-cell 32nm generation and with 4-bit-per-cell 43nm technology". Toshiba. 11 February 2009. Retrieved 21 June 2019. <a href="http://www.toshiba.co.jp/about/press/2009_02/pr1102.htm" target="_blank">http://www.toshiba.co.jp/about/press/2009_02/pr1102.htm</a> <a href="#fnref:32" class="footnote-back-ref">↩</a></li>
<li id="fn:33">"SanDisk ships world's first memory cards with 64 gigabit X4 NAND flash". SlashGear. 13 October 2009. Retrieved 20 June 2019. <a href="https://www.slashgear.com/sandisk-ships-worlds-first-memory-cards-with-64-gigabit-x4-nand-flash-1360217/" target="_blank">https://www.slashgear.com/sandisk-ships-worlds-first-memory-cards-with-64-gigabit-x4-nand-flash-1360217/</a> <a href="#fnref:33" class="footnote-back-ref">↩</a></li>
<li id="fn:34">McGlaun, Shane (2009-10-13). "SanDisk Ships World's First Memory Cards With 64 Gigabit X4 NAND Flash". SlashGear. Retrieved 2023-02-11. <a href="https://www.slashgear.com/sandisk-ships-worlds-first-memory-cards-with-64-gigabit-x4-nand-flash-1360217/" target="_blank">https://www.slashgear.com/sandisk-ships-worlds-first-memory-cards-with-64-gigabit-x4-nand-flash-1360217/</a> <a href="#fnref:34" class="footnote-back-ref">↩</a></li>
<li id="fn:35">Choi, Young (2009-05-05). "NAND Flash - The New Era of 4 bit per cell and Beyond". EE Times. Retrieved 2023-02-11. <a href="https://www.eetimes.com/nand-flash-45-the-new-era-of-4-bit-per-cell-and-beyond/" target="_blank">https://www.eetimes.com/nand-flash-45-the-new-era-of-4-bit-per-cell-and-beyond/</a> <a href="#fnref:35" class="footnote-back-ref">↩</a></li>
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</ol>

Multi-level cell open-in-new

Multi-level cell