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Power Processing Element
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<h2 id="main-features">Main features</h2> <ul><li>64-bit, dual-threaded core</li> <li>3.2 GHz typical clockrate</li> <li>32 KB <a href="/facts/CPU_cache/x8BYFcdv">L1 instruction cache</a></li> <li>32 KB <a href="/facts/CPU_cache/x8BYFcdv">L1 data cache</a></li> <li>512 KB unified L2 cache, <a href="/facts/Set-associative/MuBjrreM">8-way set associative</a> in the PPE variant.</li> <li>Compatible with 64-bit PowerPC ISA v.2.02 (<a href="/facts/POWER4/dBBnIW7g">POWER4</a> and <a href="/facts/PowerPC_970/nRyX1JxX">PowerPC 970</a>)<a class="footnote-ref" id="fnref:1" href="#fn:1"><sup>1</sup></a>: 17 </li> <li><a href="/facts/AltiVec/Vn1DY71U">AltiVec</a> <a href="/facts/SIMD/gQHWQSpo">SIMD</a> functionality</li></ul> <h2 id="execution-units">Execution units</h2> <ul><li><a href="/facts/Branch_predictor/pGPhFMj5">Branch Unit (BRU)</a></li> <li><a href="/facts/Arithmetic_logic_unit/SgIjPzSc">Fixed Point Integer Unit (FXU)</a></li> <li><a href="/facts/Load%25E2%2580%2593store_unit/8QEBxzRl">Load and Store Unit (LSU)</a></li> <li><a href="/facts/Floating-point_unit/XWTW2AbF">Floating-Point Unit (FPU)</a></li> <li><a href="/facts/AltiVec/Vn1DY71U">Vector Media Extension Unit (VMX)</a></li></ul> <h2 id="in-order">In-order</h2> <p class="note">Main article: <a href="/facts/Out-of-order_execution/bM0dQM8m">Out-of-order execution</a></p> <p>The PPU is an in-order processor, but it has some unique traits which allow it to achieve some benefits of out-of-order execution without expensive re-ordering hardware. Upon reaching an L1 cache miss – it can execute past the cache miss, stopping only when an instruction is actually dependent on a load. It can send up to 8 load instructions to the L2 cache out-of-order. It has an instruction delay pipe – a side path that allows it to execute instructions that would normally cause <a href="/facts/Bubble_(computing)/e3Ee0yJg">pipeline stalls</a> without holding up the rest of the <a href="/facts/Instruction_pipeline/3zy6CcX1">pipeline</a>. The instruction delay pipeline is used for the Out-Of-Order Load/Stores: cache misses are put there while it moves on. </p> <h2 id="the-ppes-pipeline">The PPE's pipeline</h2> <p>The PPE has a 23-stage general pipeline with an additional 11 stages possible for microcode and an additional 4 stages possible for branch prediction.<a class="footnote-ref" id="fnref:2" href="#fn:2"><sup>2</sup></a> </p> <h2 id="multithreading">Multithreading</h2> <p>The PPU runs two <a href="/facts/Simultaneous_multithreading/bk8ec9yn">hardware threads</a> simultaneously. The <a href="/facts/Processor_register/32RvbUdz">main registers</a> for code execution are duplicated, as are the exception and interrupt-handling registers, and several essential arrays and queues. They can generate exceptions simultaneously, and perform branch prediction on their individual branch histories. The execution engine and caches are not duplicated though – so it is still just a single-core design.<a class="footnote-ref" id="fnref:3" href="#fn:3"><sup>3</sup></a> </p> <h2 id="floating-point-capacity">Floating-point capacity</h2> <p>Its <a href="/facts/64-bit/AgvkQHkM">64-bit</a> <a href="/facts/Double-precision_floating-point_format/JYyXXYFM">double-precision</a> floating-point unit, and <a href="/facts/128-bit/fo1QpdNj">128-bit</a> VMX unit (using the <a href="/facts/AltiVec/Vn1DY71U">AltiVec</a> instruction set), can perform a theoretical 12 floating-point operations per cycle, as its floating-point unit can do floating-point multiply-adds, and come no smaller than 64-bits. That gives 3.2 billion clock cycles × 12 = 38.4 billion floating-point operations/second. </p><p>The PPU is enhanced in the <a href="/facts/Cell_processor/p2MIQjMc">PowerXCell 8i</a> processor to be able to make single cycle double precision floating point operations, tailored for high performance computing in supercomputers. </p><p>The VMX unit in the <a href="/facts/Xenon_(processor)/W8u6cvA2">XCPU</a> in the Xbox 360 is enhanced with 128 <a href="/facts/Processor_register/32RvbUdz">registers</a> and is not entirely compatible with regular AltiVec. </p> <h2 id="references">References</h2> <ol> <li id="fn:1"><p>Koranne, Sandeep (July 15, 2009). "The Power Processing Element (PPE)". Practical Computing on the Cell Broadband Engine. Springer Science+Business Media. pp. 17–34. doi:10.1007/978-1-4419-0308-2_2. ISBN 978-1-4419-0307-5. <a href="978-1-4419-0307-5" target="_blank">978-1-4419-0307-5</a> <a href="#fnref:1" class="footnote-back-ref">↩</a></p></li> <li id="fn:2"><p>Chen, Thomas; Raghavan, Ram; Dale, Jason; Iwata, Eiji. "Cell Broadband Engine Architecture and its first implementation". IBM DeveloperWorks. Archived from the original on 2015-12-08. <a href="https://web.archive.org/web/20151208051244/http://www.ibm.com/developerworks/library/pa-cellperf/" target="_blank">https://web.archive.org/web/20151208051244/http://www.ibm.com/developerworks/library/pa-cellperf/</a> <a href="#fnref:2" class="footnote-back-ref">↩</a></p></li> <li id="fn:3"><p>Koranne, Sandeep (July 15, 2009). "The Power Processing Element (PPE)". Practical Computing on the Cell Broadband Engine. Springer Science+Business Media. pp. 17–34. doi:10.1007/978-1-4419-0308-2_2. ISBN 978-1-4419-0307-5. <a href="978-1-4419-0307-5" target="_blank">978-1-4419-0307-5</a> <a href="#fnref:3" class="footnote-back-ref">↩</a></p></li> </ol>