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Soft microprocessor
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<h2 id="core-comparison">Core comparison</h2> <table><tbody><tr><th>Processor</th><th>Developer</th><th>Open source</th><th>Bus support</th><th>Notes</th><th>Project home</th><th>Description language</th></tr><tr><td colspan="7"><i>based on the <a href="/facts/ARM_architecture/SALsYA79">ARM</a> instruction set architecture</i></td></tr><tr><td><a href="/facts/Amber_(processor_core)/AJUgIBEY">Amber</a></td><td>Conor Santifort</td><td>LGPLv2.1</td><td><a href="/facts/Wishbone_(computer_bus)/xTu4vkDw">Wishbone</a></td><td><a href="/facts/ARM_architecture/SALsYA79">ARMv2a</a> 3-stage or 5-stage pipeline</td><td><a href="https://opencores.org/project/amber">Project page at Opencores</a></td><td>Verilog</td></tr><tr><td><a href="/facts/Cortex-M1/prW99nkV">Cortex-M1</a></td><td><a href="/facts/ARM_Holdings/jqqppj7b">ARM</a></td><td>No</td><td><a href="http://www.arm.com/products/system-ip/interconnect/index.php">[6]</a></td><td>70–200 MHz, 32-bit RISC</td><td><a href="http://www.arm.com/products/CPUs/ARM_Cortex-M1.html">[7]</a></td><td>Verilog</td></tr><tr><td colspan="7"><i>based on the <a href="/facts/AVR_microcontrollers/JvfUk4ya">AVR</a> instruction set architecture</i></td></tr><tr><td>Navré</td><td>Sébastien Bourdeauducq</td><td>Yes</td><td>Direct SRAM</td><td><a href="/facts/Atmel_AVR/JvfUk4ya">Atmel AVR</a>-compatible 8-bit RISC</td><td><a href="http://opencores.org/project,navre">Project page at Opencores</a></td><td>Verilog</td></tr><tr><td>pAVR</td><td>Doru Cuturela</td><td>Yes</td><td></td><td><a href="/facts/Atmel_AVR/JvfUk4ya">Atmel AVR</a>-compatible 8-bit RISC</td><td><a href="http://opencores.org/project,pavr">Project page at Opencores</a></td><td>VHDL</td></tr><tr><td>softavrcore</td><td>Andras Pal</td><td>Yes</td><td>Standard AVR buses (core-coupled I/O, synchronous SRAM, synchronous program ROM)</td><td><a href="/facts/Atmel_AVR/JvfUk4ya">Atmel AVR</a>-compatible 8-bit RISC (up to AVR5), peripherals and SoC features included</td><td><a href="http://opencores.org/project/softavrcore">Project page at Opencores</a></td><td>Verilog</td></tr><tr><td colspan="7"><i>based on the <a href="/facts/MicroBlaze/M0LotP1F">MicroBlaze</a> instruction set architecture</i></td></tr><tr><td>AEMB</td><td>Shawn Tan</td><td>Yes</td><td><a href="/facts/Wishbone_(computer_bus)/xTu4vkDw">Wishbone</a></td><td>MicroBlaze EDK 3.2 compatible</td><td><a href="http://www.aeste.my/aemb">AEMB</a></td><td>Verilog</td></tr><tr><td><a href="/facts/MicroBlaze/M0LotP1F">MicroBlaze</a></td><td><a href="/facts/Xilinx/rbXfxqqG">Xilinx</a></td><td>No</td><td>PLB, OPB, FSL, LMB, AXI4</td><td></td><td><a href="https://web.archive.org/web/20030430214925/http://www.xilinx.com/microblaze/">Xilinx MicroBlaze</a></td><td></td></tr><tr><td>OpenFire</td><td>Virginia Tech CCM Lab</td><td>Yes</td><td>OPB, FSL</td><td>Binary compatible with the MicroBlaze</td><td><a href="https://web.archive.org/web/20090724052731/http://www.ccm.ece.vt.edu/~scraven/openfire.html">[8]</a><a class="footnote-ref" id="fnref:12" href="#fn:12"><sup>12</sup></a></td><td>Verilog</td></tr><tr><td>SecretBlaze</td><td>LIRMM, University of Montpellier / CNRS</td><td>Yes</td><td><a href="/facts/Wishbone_(computer_bus)/xTu4vkDw">Wishbone</a></td><td>MicroBlaze ISA, VHDL</td><td><a href="http://www.lirmm.fr/ADAC/?page_id=462">SecretBlaze</a></td><td>VHDL</td></tr><tr><td colspan="7"><i>based on the <a href="/facts/MCS-51/2bqJXGlv">MCS-51</a> instruction set architecture</i></td></tr><tr><td><a href="http://www.microcorelabs.com">MCL51</a></td><td>MicroCore Labs</td><td>Yes</td><td>Ultra-small-footprint microsequencer-based 8051 core</td><td>312 Artix-7 LUTs. Quad-core 8051 version is 1227 LUTs.</td><td><a href="http://www.microcorelabs.com">MCL51 Core</a></td><td></td></tr><tr><td><a href="https://web.archive.org/web/20131008041359/http://wiki.altium.com/display/ADOH/TSK51x+MCU">TSK51/52</a></td><td><a href="/facts/Altium/TMPJ5IXb">Altium</a></td><td>Royalty-free</td><td><a href="/facts/Wishbone_(computer_bus)/xTu4vkDw">Wishbone</a> / <a href="/facts/Intel_8051/2bqJXGlv">Intel 8051</a></td><td>8-bit <a href="/facts/Intel_8051/2bqJXGlv">Intel 8051</a> instruction set compatible, lower clock cycle alternative</td><td><a href="https://web.archive.org/web/20160306202550/http://wiki.altium.com/display/adoh/processor-based+fpga+design">Embedded Design on Altium Wiki</a></td><td></td></tr><tr><td colspan="7"><i>based on the <a href="/facts/MIPS_architecture/efV4KgK4">MIPS</a> instruction set architecture</i></td></tr><tr><td><a href="http://www.cl.cam.ac.uk/research/security/ctsrd/beri/">BERI</a></td><td><a href="/facts/University_of_Cambridge/0la7aX9o">University of Cambridge</a></td><td>BSD</td><td></td><td><a href="/facts/MIPS_architecture/efV4KgK4">MIPS</a></td><td><a href="http://www.cl.cam.ac.uk/research/security/ctsrd/beri/">Project page</a></td><td><a href="/facts/Bluespec/INcoF6XJ">Bluespec</a></td></tr><tr><td><a href="http://www.dossmatik.de/mais-cpu.html">Dossmatik</a></td><td>René Doss</td><td>CC BY-NC 3.0, except <i>commercial applicants have to pay a licence fee</i>.</td><td>Pipelined bus</td><td>MIPS I instruction set pipeline stages</td><td><a href="http://www.dossmatik.de/mais-cpu.html">Dossmatik</a></td><td>VHDL</td></tr><tr><td><a href="https://web.archive.org/web/20131020113429/http://wiki.altium.com/display/ADOH/TSK3000A">TSK3000A</a></td><td><a href="/facts/Altium/TMPJ5IXb">Altium</a></td><td>Royalty-free</td><td><a href="/facts/Wishbone_(computer_bus)/xTu4vkDw">Wishbone</a></td><td>32-bit <a href="/facts/R3000/pKuMSw50">R3000</a>-style RISC modified Harvard-architecture CPU</td><td><a href="https://web.archive.org/web/20160306202550/http://wiki.altium.com/display/adoh/processor-based+fpga+design">Embedded Design on Altium Wiki</a></td><td></td></tr><tr><td colspan="7"><i>based on the <a href="/facts/PicoBlaze/SW3fCRxD">PicoBlaze</a> instruction set architecture</i></td></tr><tr><td>PacoBlaze</td><td>Pablo Bleyer</td><td>Yes</td><td></td><td>Compatible with the PicoBlaze processors</td><td><a href="http://bleyer.org/pacoblaze">PacoBlaze</a></td><td>Verilog</td></tr><tr><td><a href="/facts/PicoBlaze/SW3fCRxD">PicoBlaze</a></td><td><a href="/facts/Xilinx/rbXfxqqG">Xilinx</a></td><td>No</td><td></td><td></td><td><a href="https://web.archive.org/web/20030501203653/http://www.xilinx.com/picoblaze/">Xilinx PicoBlaze</a></td><td>VHDL, Verilog</td></tr><tr><td colspan="7"><i>based on the <a href="/facts/RISC-V/pUSKDat1">RISC-V</a> instruction set architecture</i></td></tr><tr><td><a href="https://github.com/f32c/f32c">f32c</a></td><td>University of Zagreb</td><td>BSD</td><td>AXI, SDRAM, SRAM</td><td>32-bit, RISC-V / MIPS ISA subsets (retargetable), GCC toolchain</td><td><a href="https://github.com/f32c/f32c">f32c</a></td><td>VHDL</td></tr><tr><td><a href="https://github.com/stnolting/neorv32">NEORV32</a></td><td>Stephan Nolting</td><td>BSD</td><td>Wishbone b4, AXI4</td><td>rv32[i/e] [m] [a] [c] [b] [u] [Zfinx] [Zicsr] [Zifencei], RISC-V-compliant, CPU & SoC available, highly customizable, GCC toolchain</td><td><a href="https://github.com/stnolting/neorv32">GitHub</a> <a href="https://opencores.org/projects/neorv32">OpenCores</a></td><td>VHDL</td></tr><tr><td>VexRiscv</td><td>SpinalHDL</td><td>Yes</td><td>AXI4 / Avalon</td><td>32-bit, RISC-V, up to 340 MHz on Artix 7. Up to 1.44 DMIPS/MHz.</td><td><a href="https://github.com/SpinalHDL/VexRiscv">https://github.com/SpinalHDL/VexRiscv</a></td><td>VHDLVerilog (SpinalHDL)</td></tr><tr><td colspan="7"><i>based on the <a href="/facts/SPARC/m7KhEtET">SPARC</a> instruction set architecture</i></td></tr><tr><td><a href="/facts/LEON/6Lxp8yNm">LEON2(-FT)</a></td><td><a href="/facts/European_Space_Agency/L8YRNV0C">ESA</a></td><td>Yes</td><td>AMBA2</td><td>SPARC V8</td><td><a href="http://www.esa.int/TEC/Microelectronics/SEMUD70CYTE_0.html">ESA</a></td><td>VHDL</td></tr><tr><td><a href="/facts/LEON/6Lxp8yNm">LEON3/4</a></td><td>Aeroflex Gaisler</td><td>Yes</td><td>AMBA2</td><td>SPARC V8</td><td><a href="http://www.gaisler.com/cms/index.php?option=com_content&task=view&id=156&Itemid=104">Aeroflex Gaisler</a></td><td>VHDL</td></tr><tr><td><a href="http://parallel.princeton.edu/openpiton/specs.html">OpenPiton</a></td><td>Princeton Parallel Group</td><td>Yes</td><td></td><td><a href="/facts/Manycore_processor/ozoxeNzT">Manycore</a> <a href="/facts/SPARC/m7KhEtET">SPARC V9</a></td><td><a href="http://parallel.princeton.edu/openpiton/specs.html">OpenPiton</a></td><td>Verilog</td></tr><tr><td><a href="/facts/OpenSPARC/6cokbgCP">OpenSPARC T1</a></td><td><a href="/facts/Sun_Microsystems/VJ9EzEFd">Sun</a></td><td>Yes</td><td></td><td>64-bit</td><td><a href="http://www.opensparc.net/opensparc-t1/index.html">OpenSPARC.net</a></td><td>Verilog</td></tr><tr><td>Tacus/PIPE5</td><td>TemLib</td><td>Yes</td><td>Pipelined bus</td><td>SPARC V8</td><td><a href="http://temlib.org">TEMLIB</a></td><td>VHDL</td></tr><tr><td colspan="7"><i>based on the <a href="/facts/X86/Kypq5fgu">x86</a> instruction set architecture</i></td></tr><tr><td>CPU86</td><td>HT-Lab</td><td>Yes</td><td></td><td>8088-compatible CPU in VHDL</td><td><a href="http://www.ht-lab.com/cpu86.htm">cpu86</a></td><td>VHDL</td></tr><tr><td><a href="http://www.microcorelabs.com">MCL86</a></td><td>MicroCore Labs</td><td>Yes</td><td>8088 BIU provided. Others easy to create.</td><td>Cycle accurate 8088/8086 implemented with a microsequencer. Less than 2% utilization of Kintex-7.</td><td><a href="http://www.microcorelabs.com">MCL86 Core</a></td><td></td></tr><tr><td><a href="https://www.jamieiles.com/80186/">s80x86</a></td><td>Jamie Iles</td><td>GPLv3</td><td>Custom</td><td>80186-compatible GPLv3 core</td><td><a href="https://www.jamieiles.com/80186/">s80x86</a></td><td>SystemVerilog</td></tr><tr><td>Zet</td><td>Zeus Gómez Marmolejo</td><td>Yes</td><td><a href="/facts/Wishbone_(computer_bus)/xTu4vkDw">Wishbone</a></td><td>x86 PC clone</td><td><a href="https://archive.today/20130112150552/http://zet.aluzina.org/">Zet</a></td><td>Verilog</td></tr><tr><td>ao486</td><td>Aleksander Osman</td><td>3-Clause BSD</td><td>Avalon</td><td>i486 SX compatible core</td><td><a href="https://github.com/alfikpl/ao486">ao486</a></td><td>Verilog</td></tr><tr><td colspan="7"><i>based on the <a href="/facts/Power_ISA/GLy1WS0m">PowerPC/Power</a> instruction set architecture</i></td></tr><tr><td><a href="/facts/PowerPC_400/X6zS1Rgu">PowerPC 405S</a></td><td>IBM</td><td>No</td><td><a href="/facts/CoreConnect/FVyXCn40">CoreConnect</a></td><td>32-bit PowerPC v.2.03 Book E</td><td><a href="/facts/IBM/QszA7nwd">IBM</a></td><td>Verilog</td></tr><tr><td><a href="/facts/PowerPC_400/X6zS1Rgu">PowerPC 440S</a></td><td>IBM</td><td>No</td><td><a href="/facts/CoreConnect/FVyXCn40">CoreConnect</a></td><td>32-bit PowerPC v.2.03 Book E</td><td><a href="/facts/IBM/QszA7nwd">IBM</a></td><td>Verilog</td></tr><tr><td><a href="/facts/PowerPC_400/X6zS1Rgu">PowerPC 470S</a></td><td>IBM</td><td>No</td><td><a href="/facts/CoreConnect/FVyXCn40">CoreConnect</a></td><td>32-bit PowerPC v.2.05 Book E</td><td><a href="/facts/IBM/QszA7nwd">IBM</a></td><td>Verilog</td></tr><tr><td><a href="/facts/OpenPower_Microwatt/TCbopn4u">Microwatt</a></td><td>IBM/OpenPOWER</td><td>CC-BY 4.0</td><td><a href="/facts/Wishbone_(computer_bus)/xTu4vkDw">Wishbone</a></td><td>64-bit PowerISA 3.0 proof of concept</td><td><a href="https://github.com/antonblanchard/microwatt">Microwatt @ Github</a></td><td>VHDL</td></tr><tr><td><a href="/facts/OpenPower_Microwatt/TCbopn4u">Chiselwatt</a></td><td>IBM/OpenPOWER</td><td>CC-BY 4.0</td><td><a href="/facts/Wishbone_(computer_bus)/xTu4vkDw">Wishbone</a></td><td>64-bit PowerISA 3.0</td><td><a href="https://github.com/antonblanchard/chiselwatt">Chiselwatt @ Github</a></td><td>Chisel</td></tr><tr><td><a href="/facts/Libre-SOC/uKm3wH7Y">Libre-SOC</a></td><td><a href="https://libre-soc.org">Libre-SoC.org</a></td><td>BSD/LGPLv2+</td><td><a href="/facts/Wishbone_(computer_bus)/xTu4vkDw">Wishbone</a></td><td>64-bit PowerISA 3.0. CPU/GPU/VPU implementation and custom vector instructions</td><td><a href="https://libre-soc.org">Libre-SoC.org</a></td><td>python/nMigen</td></tr><tr><td><a href="/facts/IBM_A2/o4VHVJE8">A2I</a></td><td>IBM/OpenPOWER</td><td>CC-BY 4.0</td><td>Custom PBus</td><td>64-bit PowerPC 2.6 Book E. In order core</td><td><a href="https://github.com/openpower-cores/a2i">A2I @ Github</a></td><td>VHDL</td></tr><tr><td><a href="/facts/IBM_A2/o4VHVJE8">A2O</a></td><td>IBM/OpenPOWER</td><td>CC-BY 4.0</td><td>Custom PBus</td><td>64-bit PowerPC 2.7 Book E. Out of order core</td><td><a href="https://github.com/openpower-cores/a2o">A2O @ Github</a></td><td>Verilog</td></tr><tr><td colspan="7"><i>Other architectures</i></td></tr><tr><td><a href="/facts/ARC_(processor)/oFXJYBNR">ARC</a></td><td><a href="/facts/Synopsys/Szv1V36J">ARC International</a>, <a href="/facts/Synopsys/Szv1V36J">Synopsys</a></td><td>No</td><td></td><td>16/32/64-bit ISA RISC</td><td><a href="https://www.synopsys.com/designware-ip/processor-solutions.html">DesignWare ARC</a></td><td>Verilog</td></tr><tr><td>ERIC5</td><td>Entner Electronics</td><td>No</td><td></td><td>9-bit RISC, very small size, C-programmable</td><td><a href="http://www.entner-electronics.com/tl/index.php/eric5.html">ERIC5</a> <a href="https://web.archive.org/web/20160305131214/http://www.entner-electronics.com/tl/index.php/eric5.html">Archived</a> 2016-03-05 at the <a href="/facts/Wayback_Machine/nmQ3a6JC">Wayback Machine</a></td><td>VHDL</td></tr><tr><td><a href="https://github.com/howerj/forth-cpu">H2 CPU</a></td><td>Richard James Howe</td><td>MIT</td><td>Custom</td><td>16-bit Stack Machine, designed to execute Forth directly, small</td><td><a href="https://github.com/howerj/forth-cpu">H2 CPU</a></td><td>VHDL</td></tr><tr><td><a href="http://www.fpga-cores.com/instant-soc/">Instant SoC</a></td><td><a href="http://www.fpga-cores.com/">FPGA Cores</a></td><td>No</td><td>Custom</td><td>32-bit RISC-V M Extension, SoC defined by C++</td><td><a href="http://www.fpga-cores.com/instant-soc/">Instant SoC</a></td><td>VHDL</td></tr><tr><td><a href="/facts/Java_optimized_processor/pHWsKQ0Y">JOP</a></td><td>Martin Schoeberl</td><td>Yes</td><td>SimpCon / <a href="/facts/Wishbone_(computer_bus)/xTu4vkDw">Wishbone</a> (extension)</td><td>Stack-oriented, hard real-time support, executing <a href="/facts/Java_bytecode/Nh1qKH4y">Java bytecode</a> directly</td><td><a href="https://web.archive.org/web/20190417225405/http://www.jopdesign.com/">Jop</a></td><td>VHDL</td></tr><tr><td><a href="/facts/LatticeMico8/1KuDyqVM">LatticeMico8</a></td><td><a href="/facts/Lattice_Semiconductor/aPJY9jNu">Lattice</a></td><td>Yes</td><td><a href="/facts/Wishbone_(computer_bus)/xTu4vkDw">Wishbone</a></td><td></td><td><a href="http://www.latticesemi.com/Products/DesignSoftwareAndIP/IntellectualProperty/IPCore/IPCores02/Mico8.aspx">LatticeMico8</a></td><td>Verilog</td></tr><tr><td><a href="/facts/LatticeMico32/5KXwoTol">LatticeMico32</a></td><td><a href="/facts/Lattice_Semiconductor/aPJY9jNu">Lattice</a></td><td>Yes</td><td><a href="/facts/Wishbone_(computer_bus)/xTu4vkDw">Wishbone</a></td><td></td><td><a href="http://www.latticesemi.com/products/intellectualproperty/ipcores/mico32/index.cfm">LatticeMico32</a></td><td>Verilog</td></tr><tr><td><a href="https://lxp32.github.io/">LXP32</a></td><td>Alex Kuznetsov</td><td>MIT</td><td><a href="/facts/Wishbone_(computer_bus)/xTu4vkDw">Wishbone</a></td><td>32-bit, 3-stage pipeline, <a href="/facts/Register_file/NGvqUwe3">register file</a> based on block RAM</td><td><a href="https://lxp32.github.io/">lxp32</a></td><td>VHDL</td></tr><tr><td><a href="https://github.com/MicroCoreLabs/Projects">MCL65</a></td><td>MicroCore Labs</td><td>Yes</td><td>Ultra-small-footprint microsequencer-based 6502 core</td><td>252 Spartan-7 LUTs. Clock cycle-exact.</td><td><a href="https://github.com/MicroCoreLabs/Projects">MCL65 Core</a></td><td></td></tr><tr><td><a href="https://mrisc32.bitsnbites.eu/">MRISC32-A1</a></td><td>Marcus Geelnard</td><td>Yes</td><td><a href="/facts/Wishbone_(computer_bus)/xTu4vkDw">Wishbone</a>, B4/pipelined</td><td>32-bit RISC/Vector CPU implementing the MRISC32 ISA</td><td><a href="https://mrisc32.bitsnbites.eu/">MRISC32</a></td><td>VHDL</td></tr><tr><td><a href="https://github.com/stnolting/neo430">NEO430</a></td><td>Stephan Nolting</td><td>Yes</td><td>Wishbone (Avalon, AXI4-Lite)</td><td>16-bit MSP430 ISA-compatible, very small size, many peripherals, highly customizable</td><td><a href="https://github.com/stnolting/neo430">NEO430</a></td><td>VHDL</td></tr><tr><td><a href="/facts/Nios_embedded_processor/MelW9MsJ">Nios</a>, <a href="/facts/Nios_II/sbFl05Wx">Nios II</a></td><td><a href="/facts/Altera/66c0Gh0R">Altera</a></td><td>No</td><td>Avalon</td><td></td><td><a href="https://web.archive.org/web/20101225092752/http://www.altera.com/products/ip/processors/nios2/ni2-index.html">Altera Nios II</a></td><td>Verilog</td></tr><tr><td><a href="/facts/OpenRISC/G40wlEKP">OpenRISC</a></td><td><a href="/facts/OpenCores/I4qbrRUP">OpenCores</a></td><td>Yes</td><td><a href="/facts/Wishbone_(computer_bus)/xTu4vkDw">Wishbone</a></td><td>32-bit; done in ASIC, Actel, Altera, Xilinx FPGA.</td><td><a href="https://openrisc.io/">[9]</a></td><td>Verilog</td></tr><tr><td>SpartanMC</td><td>TU Darmstadt / TU Dresden</td><td>Yes</td><td>Custom (<a href="/facts/Advanced_eXtensible_Interface/6HMbWKTN">AXI</a> support in development)</td><td>18-bit ISA (GNU Binutils / GCC support in development)</td><td><a href="http://www.spartanmc.de">SpartanMC</a></td><td>Verilog</td></tr><tr><td>SYNPIC12</td><td>Miguel Angel Ajo Pelayo</td><td>MIT</td><td></td><td>PIC12F compatible, program synthesised in gates</td><td><a href="http://projects.nbee.es/display/IPCORES/SYNPIC12+8bit+RISC+CPU+core">nbee.es</a></td><td>VHDL</td></tr><tr><td>xr16</td><td>Jan Gray</td><td>No</td><td>XSOC abstract bus</td><td>16-bit RISC CPU and SoC featured in Circuit Cellar Magazine #116-118</td><td><a href="http://www.fpgacpu.org/xsoc/index.html">XSOC/xr16</a></td><td>Schematic</td></tr><tr><td>YASEP</td><td>Yann Guidon</td><td>AGPLv3</td><td>Direct SRAM</td><td>16 or 32 bits, RTL in <a href="https://web.archive.org/web/20121207045204/http://yasep.org/VHDL/">VHDL</a> & <a href="http://yasep.org/#!ASM/impASM#examples/keywords.yas">asm</a> in <a href="/facts/JavaScript/XhhIIEsl">JS</a>, microcontroller subset : ready</td><td><a href="http://yasep.org">yasep.org</a> (<a href="http://www.mozilla.com/">Firefox</a> required)</td><td>VHDL</td></tr><tr><td><a href="http://zipcpu.com/about/zipcpu.html">ZipCPU</a></td><td><a href="http://zipcpu.com/about/gisselquist-technology.html">Gisselquist Technology</a></td><td>GPLv3</td><td>Wishbone, B4/pipelined</td><td>32-bit CPU targeted for minimal FPGA resource usage</td><td><a href="http://zipcpu.com/about/zipcpu.html">zipcpu.com</a></td><td>Verilog</td></tr><tr><td><a href="/facts/ZPU_(microprocessor)/uJpW4nf1">ZPU</a></td><td>Zylin AS</td><td>Yes</td><td><a href="/facts/Wishbone_(computer_bus)/xTu4vkDw">Wishbone</a></td><td>Stack based CPU, configurable 16/32 bit datapath, <a href="/facts/ECos/oegwUbDy">eCos</a> support</td><td><a href="http://opensource.zylin.com/zpu.htm">Zylin CPU</a></td><td>VHDL</td></tr><tr><td>RISC5</td><td>Niklaus Wirth</td><td>Yes</td><td>Custom</td><td>Running a complete graphical Oberon System including an editor and compiler. Software can be developed and ran on the same FPGA board.</td><td><a href="http://www.projectoberon.com/">www.projectoberon.com/</a></td><td>Verilog</td></tr></tbody></table> <h2 id="see-also">See also</h2> <ul><li><a href="/facts/System_on_a_chip/1RVvVe6N">System-on-a-chip</a> (SoC) <ul><li><a href="/facts/Network_on_a_chip/yES3YXp0">Network-on-a-chip</a> (NoC)</li></ul></li> <li><a href="/facts/Reconfigurable_computing/J4b2JsRB">Reconfigurable computing</a> <ul><li><a href="/facts/Field-programmable_gate_array/M8LSGcAU">Field-programmable gate array</a> (FPGA)</li></ul></li> <li><a href="/facts/VHDL/H6Exdjfs">VHDL</a></li> <li><a href="/facts/Verilog/efVqbKXg">Verilog</a> <ul><li><a href="/facts/SystemVerilog/wkBdc179">SystemVerilog</a></li></ul></li> <li><a href="/facts/Hardware_acceleration/ej5sM7hB">Hardware acceleration</a></li></ul> <h2 id="external-links">External links</h2> <ul><li><a href="https://web.archive.org/web/20091026171102/http://1-core.com/library/digital/soft-cpu-cores/">Soft CPU Cores for FPGA</a></li> <li><a href="https://web.archive.org/web/20070615082550/http://www.ews.uiuc.edu/~pdabrows/soft_processor_comparison.html">Detailed Comparison of 12 Soft Microprocessors</a></li> <li><a href="http://www.fpgacpu.org">FPGA CPU News</a></li> <li><a href="http://f-cpu.org">Freedom CPU website</a></li> <li><a href="http://opencores.org/projects">Microprocessor cores</a> on Opencores.org (Expand the "Processor" tab)</li> <li><a href="http://www.niktech.com">NikTech</a> 32 bit RISC Microprocessor MANIK.</li></ul> <h2 id="references">References</h2> <ol> <li id="fn:1"><p>Article title[usurped] "Zet soft core running Windows 3.0" by Andrew Felch 2011 <a href="https://web.archive.org/web/20181013095941/http://www.dailycircuitry.com/2011/10/zet-soft-core-running-windows-30.html" target="_blank">https://web.archive.org/web/20181013095941/http://www.dailycircuitry.com/2011/10/zet-soft-core-running-windows-30.html</a> <a href="#fnref:1" class="footnote-back-ref">↩</a></p></li> <li id="fn:2"><p>"Embedded.com - FPGA Architectures from 'A' to 'Z' : Part 2". Archived from the original on 2007-10-08. Retrieved 2012-08-18. "FPGA Architectures from 'A' to 'Z'" by Clive Maxfield 2006 <a href="https://web.archive.org/web/20071008163016/http://www.embedded.com/columns/showArticle.jhtml?articleID=192700615" target="_blank">https://web.archive.org/web/20071008163016/http://www.embedded.com/columns/showArticle.jhtml?articleID=192700615</a> <a href="#fnref:2" class="footnote-back-ref">↩</a></p></li> <li id="fn:3"><p>MicroBlaze Soft Processor: Frequently Asked Questions Archived 2011-10-27 at the Wayback Machine <a href="http://www.xilinx.com/products/design_resources/proc_central/microblaze_faq.pdf" target="_blank">http://www.xilinx.com/products/design_resources/proc_central/microblaze_faq.pdf</a> <a href="#fnref:3" class="footnote-back-ref">↩</a></p></li> <li id="fn:4"><p>István Vassányi. "Implementing processor arrays on FPGAs". 1998. [1] <a href="https://doi.org/10.1007%2FBFb0055278" target="_blank">https://doi.org/10.1007%2FBFb0055278</a> <a href="#fnref:4" class="footnote-back-ref">↩</a></p></li> <li id="fn:5"><p>Zhoukun WANG and Omar HAMMAMI. "A 24 Processors System on Chip FPGA Design with Network on Chip". [2] <a href="http://www.design-reuse.com/articles/21583/processor-noc-fpga.html" target="_blank">http://www.design-reuse.com/articles/21583/processor-noc-fpga.html</a> <a href="#fnref:5" class="footnote-back-ref">↩</a></p></li> <li id="fn:6"><p>John Kent. "Micro16 Array - A Simple CPU Array" [3] <a href="http://members.optusnet.com.au/jekent/Micro16Array/index.html" target="_blank">http://members.optusnet.com.au/jekent/Micro16Array/index.html</a> <a href="#fnref:6" class="footnote-back-ref">↩</a></p></li> <li id="fn:7"><p>Kit Eaton. "1,000 Core CPU Achieved: Your Future Desktop Will Be a Supercomputer". 2011. [4] <a href="http://www.fastcompany.com/1714174/1000-core-cpu-achieved-your-future-desktop-will-be-a-supercomputer?partner=rss" target="_blank">http://www.fastcompany.com/1714174/1000-core-cpu-achieved-your-future-desktop-will-be-a-supercomputer?partner=rss</a> <a href="#fnref:7" class="footnote-back-ref">↩</a></p></li> <li id="fn:8"><p>"Scientists Squeeze Over 1,000 Cores onto One Chip". 2011. [5] Archived 2012-03-05 at the Wayback Machine <a href="http://www.ecnmag.com/news/2011/01/research/Over-1000-Cores-on-One-Chip.aspx" target="_blank">http://www.ecnmag.com/news/2011/01/research/Over-1000-Cores-on-One-Chip.aspx</a> <a href="#fnref:8" class="footnote-back-ref">↩</a></p></li> <li id="fn:9"><p>Joe DeLaere. ""Top 7 Reasons to Replace Your Microcontroller with a MAX 10 FPGA"" (PDF). <a href="https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/wp/wp-01255-top-7-reasons-to-replace-your-microcontroller-with-a-max-10-fpga.pdf" target="_blank">https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/wp/wp-01255-top-7-reasons-to-replace-your-microcontroller-with-a-max-10-fpga.pdf</a> <a href="#fnref:9" class="footnote-back-ref">↩</a></p></li> <li id="fn:10"><p>John Swan; Tomek Krzyzak. (2008). ""Using FPGAs to avoid microprocessor obsolescence"". Archived from the original on 2016-10-13. <a href="https://web.archive.org/web/20161013004106/http://www.embedded.com/print/4015159" target="_blank">https://web.archive.org/web/20161013004106/http://www.embedded.com/print/4015159</a> <a href="#fnref:10" class="footnote-back-ref">↩</a></p></li> <li id="fn:11"><p>Staff (2010-02-03). "FPGA processor IP needs to be supported". Electronics Weekly. Retrieved 2019-04-03. <a href="https://www.electronicsweekly.com/news/products/fpga-news/fpga-processor-ip-needs-to-be-supported-2010-02/" target="_blank">https://www.electronicsweekly.com/news/products/fpga-news/fpga-processor-ip-needs-to-be-supported-2010-02/</a> <a href="#fnref:11" class="footnote-back-ref">↩</a></p></li> <li id="fn:12"><p>"Overview :: OpenFire Processor Core :: OpenCores". <a href="http://opencores.org/project,openfire_core,overview" target="_blank">http://opencores.org/project,openfire_core,overview</a> <a href="#fnref:12" class="footnote-back-ref">↩</a></p></li> </ol>