SHA instruction set

<h2 id="x86-architecture-processors">x86 architecture processors</h2>
<p>The original <a href="/facts/Streaming_SIMD_Extensions/mMa6EFyB">SSE</a>-based extensions added four instructions supporting <a href="/facts/SHA-1/LDYCV1je">SHA-1</a> and three for <a href="/facts/SHA-256/P59oPeGq">SHA-256</a>.
</p>
<ul><li>SHA-1: SHA1RNDS4, SHA1NEXTE, SHA1MSG1, SHA1MSG2</li>
<li>SHA-256: SHA256RNDS2, SHA256MSG1, SHA256MSG2</li></ul>
<p>The newer SHA-512 instruction set comprises <a href="/facts/Advanced_Vector_Extensions/znDpc6Vt">AVX</a>-based versions of the original SHA <a href="/facts/Instruction_set/8p8vwUeE">instruction set</a> marked with a V prefix and these three new AVX-based instructions for <a href="/facts/SHA-512/P59oPeGq">SHA-512</a>:
</p>
<ul><li>VSHA512RNDS2, VSHA512MSG1, VSHA512MSG2</li></ul>
<h3>AMD</h3>
<p>All recent AMD processors support the original SHA instruction set:
</p>
<ul><li>AMD <a href="/facts/Zen_(microarchitecture)/AjBvqDT7">Zen</a><a class="footnote-ref" id="fnref:2" href="#fn:2"><sup>2</sup></a> (2017) and later processors.</li></ul>
<h3>Intel</h3>
<p>The following Intel processors support the original SHA instruction set:
</p>
<ul><li>Intel <a href="/facts/Goldmont/hJSdoIJq">Goldmont</a><a class="footnote-ref" id="fnref:3" href="#fn:3"><sup>3</sup></a> (2016) and later Atom microarchitecture processors.</li>
<li>Intel <a href="/facts/Cannon_Lake_(microarchitecture)/GN2Ixtzr">Cannon Lake</a><a class="footnote-ref" id="fnref:4" href="#fn:4"><sup>4</sup></a> (2018/2019), <a href="/facts/Ice_Lake_(microarchitecture)/ezzrBUW5">Ice Lake</a><a class="footnote-ref" id="fnref:5" href="#fn:5"><sup>5</sup></a> (2019) and later processors for laptops ("mainstream mobile").</li>
<li>Intel <a href="/facts/Rocket_Lake/e9xcN1Yk">Rocket Lake</a> (2021) and later processors for desktop computers.</li></ul>
<p>The following Intel processors will support the newer SHA-512 instruction set:
</p>
<ul><li>Intel <a href="/facts/Arrow_Lake_(microprocessor)/AFTvbCBU">Arrow Lake</a> and <a href="/facts/Lunar_Lake/LAyQmrEB">Lunar Lake</a> processors.</li></ul>

<h2 id="external-links">External links</h2>
<ul><li>Chapter 8 of <a href="https://web.archive.org/web/20130929035331/http://download-software.intel.com/sites/default/files/319433-015.pdf">"Intel Architecture Instruction Set Extensions Programming Reference"</a> (PDF). Archived from <a href="http://download-software.intel.com/sites/default/files/319433-015.pdf">the original</a> (PDF) on 2013-09-29.</li></ul>

<h2 id="references">References</h2>

<ol>
<li id="fn:1"><p>"New Instructions Supporting the Secure Hash Algorithm on Intel® Architecture Processors". intel.com. Retrieved 2024-07-25. <a href="https://software.intel.com/en-us/articles/intel-sha-extensions" target="_blank">https://software.intel.com/en-us/articles/intel-sha-extensions</a> <a href="#fnref:1" class="footnote-back-ref">↩</a></p></li>
<li id="fn:2"><p>"Zen - Microarchitectures - AMD - WikiChip". en.wikichip.org. Retrieved 2024-07-25. <a href="https://en.wikichip.org/wiki/amd/microarchitectures/zen#New_instructions" target="_blank">https://en.wikichip.org/wiki/amd/microarchitectures/zen#New_instructions</a> <a href="#fnref:2" class="footnote-back-ref">↩</a></p></li>
<li id="fn:3"><p>"Goldmont - Microarchitectures - Intel - WikiChip". en.wikichip.org. Retrieved 2024-07-25. <a href="https://en.wikichip.org/wiki/intel/microarchitectures/goldmont#New_instructions" target="_blank">https://en.wikichip.org/wiki/intel/microarchitectures/goldmont#New_instructions</a> <a href="#fnref:3" class="footnote-back-ref">↩</a></p></li>
<li id="fn:4"><p>"Cannon Lake - Microarchitectures - Intel - WikiChip". en.wikichip.org. Retrieved 2024-07-25. <a href="https://en.wikichip.org/wiki/intel/microarchitectures/cannon_lake#New_instructions" target="_blank">https://en.wikichip.org/wiki/intel/microarchitectures/cannon_lake#New_instructions</a> <a href="#fnref:4" class="footnote-back-ref">↩</a></p></li>
<li id="fn:5"><p>"Ice Lake (client) - Microarchitectures - Intel - WikiChip". en.wikichip.org. Retrieved 2024-07-25. <a href="https://en.wikichip.org/wiki/intel/microarchitectures/ice_lake_(client)#New_instructions" target="_blank">https://en.wikichip.org/wiki/intel/microarchitectures/ice_lake_(client)#New_instructions</a> <a href="#fnref:5" class="footnote-back-ref">↩</a></p></li>
</ol>

SHA instruction set open-in-new

SHA instruction set