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<h2 id="example-assembler-syntax">Example assembler syntax</h2> <table><tbody><tr><td><a href="/facts/MSP430/ngwhqtNN">MSP430</a>: </td><td>br r15</td></tr><tr><td><a href="/facts/SPARC/m7KhEtET">SPARC</a>: </td><td>jmpl %o7</td></tr><tr><td><a href="/facts/MIPS_architecture/efV4KgK4">MIPS</a>: </td><td>jr $ra</td></tr><tr><td><a href="/facts/X86/Kypq5fgu">x86</a> (AT&T Syntax): </td><td>jmp *%eax</td></tr><tr><td><a href="/facts/X86/Kypq5fgu">x86</a> (Intel Syntax): </td><td>jmp eax</td></tr><tr><td><a href="/facts/ARM_architecture/SALsYA79">ARM</a>: </td><td>BX r0, mov pc, r2</td></tr><tr><td><a href="/facts/Itanium/0wkjSDpe">Itanium</a> (x86 family): </td><td>br.ret.sptk.few rp</td></tr><tr><td><a href="/facts/6502/q9YLwkzm">6502</a>: </td><td>jmp ($0DEA)</td></tr><tr><td><a href="/facts/65C816/5Ce9Nh4P">65C816</a>: </td><td>jsr ($0DEA,X)</td></tr><tr><td><a href="/facts/6809/AM6UosAk">6809</a>: </td><td>jmp [$0DEA], jmp B,X, jmp [B,X]</td></tr><tr><td><a href="/facts/Motorola_6800/0D4BNIha">6800</a>: </td><td>jmp 0,X</td></tr><tr><td><a href="/facts/Z80/Jeqe2h55">Z80</a>: </td><td>jp (hl)</td></tr><tr><td><a href="/facts/Intel_MCS-51/2bqJXGlv">Intel MCS-51</a>: </td><td>jmp @A+DPTR</td></tr><tr><td><a href="/facts/Intel_8080/32FvNTcD">Intel 8080</a>: </td><td>pchl</td></tr><tr><td><a href="/facts/IBM_System_z/JJX9eAsD">IBM System z</a>: </td><td>bcr cond,r1<a class="footnote-ref" id="fnref:3" href="#fn:3"><sup>3</sup></a></td></tr><tr><td><a href="/facts/PDP-11_architecture/ftdFDdcp">PDP-11</a>: </td><td>jmp @R5</td></tr><tr><td><a href="/facts/RISC-V/pUSKDat1">RISC-V</a>:</td><td>jalr x0, 0(x1)</td></tr></tbody></table> <h2 id="see-also">See also</h2> <ul><li><a href="/facts/Branch_table/LcfPVyQS">Branch table</a></li> <li><a href="/facts/Indirect_threading/RwL3h6DJ">Indirect threading</a></li> <li><a href="/facts/Indirect_branch_control/BdbdpdgB">Indirect branch control</a> (IBC)</li> <li><a href="/facts/Indirect_branch_restricted_speculation/BdbdpdgB">Indirect branch restricted speculation</a> (IBRS)</li> <li><a href="/facts/Indirect_branch_prediction_barrier/BdbdpdgB">Indirect branch prediction barrier</a> (IBPB)</li> <li><a href="/facts/Single_thread_indirect_branch_predictor/BdbdpdgB">Single thread indirect branch predictor</a> (STIBP)</li></ul> <h2 id="notes">Notes</h2> <h2 id="references">References</h2> <ol> <li id="fn:1"><p>Larabel, Michael (2018-01-14). "Spectre Mitigation Added To GCC 8, Seeking Backport To GCC 7". Archived from the original on 2018-01-20. Retrieved 2018-01-19. <a href="/wiki/Michael_Larabel" target="_blank">/wiki/Michael_Larabel</a> <a href="#fnref:1" class="footnote-back-ref">↩</a></p></li> <li id="fn:2"><p>Consult also the RETPOLINE=y feature added in Linux kernel 4.14.14/4.9.77/4.4.112. See also: Retpoline <a href="/wiki/Retpoline" target="_blank">/wiki/Retpoline</a> <a href="#fnref:2" class="footnote-back-ref">↩</a></p></li> <li id="fn:3"><p>"z/Architecture - Principles of Operation" (4 ed.). IBM. May 2004 [1990]. SA22-7832-03. Archived from the original on 2016-03-04. Retrieved 2018-05-26. <a href="http://www-01.ibm.com/support/docview.wss?uid=isg26480faec85f44e2385256d5200627dee&aid=1" target="_blank">http://www-01.ibm.com/support/docview.wss?uid=isg26480faec85f44e2385256d5200627dee&aid=1</a> <a href="#fnref:3" class="footnote-back-ref">↩</a></p></li> </ol>