Nios II

<h2 id="key-features">Key features</h2>
<p>Like the original Nios, the Nios II architecture is a <a href="/facts/RISC/aQbGM62p">RISC</a> <a href="/facts/Soft_microprocessor/pCmb601M">soft-core</a> architecture which is implemented entirely in the programmable logic and memory blocks of Altera FPGAs. Unlike its predecessor it is a full <a href="/facts/32-bit_computing/TDMVce8s">32-bit</a> design:
</p>
<ul><li>32 general-purpose 32-bit registers,</li>
<li>Full 32-bit instruction set, data path, and address space,</li>
<li>Single-instruction 32 × 32 multiply and divide producing a 32-bit result.</li></ul>
<p>The soft-core nature of the Nios II processor lets the system designer specify and generate a custom Nios II core, tailored for his or her specific application requirements. System designers can extend the Nios II's basic functionality by, for example, adding a predefined memory management unit, or defining custom instructions and custom peripherals.
</p>
<h3>Custom instructions</h3>
<p>Similar to native Nios II instructions, user-defined instructions accept values from up to two 32-<a href="/facts/Bit/S972NSaD">bit</a> source registers and optionally write back a result to a 32-bit destination register. By using custom instructions, the system designers can fine-tune the system hardware to meet performance goals and also the designer can easily handle the instruction as a macro in <a href="/facts/C_(programming_language)/Ky2No763">C</a>.
</p>
<h3>Custom peripherals</h3>
<p>For performance-critical systems that spend most CPU cycles executing a specific section of code, a user-defined peripheral can potentially offload part or all of the execution of a software-algorithm to user-defined <a href="/facts/Hardware_logic/fKcrTv2f">hardware logic</a>, improving power-efficiency or application throughput.
</p>
<h3>Memory Management Unit</h3>
<p>Introduced with <a href="/facts/Altera_Quartus/28K9Nq7M">Quartus</a> 8.0, the optional MMU enables Nios II to run operating systems which require hardware-based paging and protection, such as the Linux kernel. Without an MMU, Nios is restricted to operating systems which use a simplified protection and virtual memory-model: e.g., <a href="/facts/%25CE%259CClinux/jSjp2fEF">μClinux</a> and <a href="/facts/FreeRTOS/v9how6mE">FreeRTOS</a>.
</p>
<h3>Memory Protection Unit</h3>
<p>Introduced with Quartus 8.0, the optional MPU provides memory protection similar to that provided by an MMU but with a simpler programming model and without the performance overhead associated with an MMU.
</p>
<h2 id="nios-ii-cpu-family">Nios II CPU family</h2>
<p>Nios II classic is offered in 3 different configurations: Nios II/f (fast), Nios II/s (standard), and Nios II/e (economy).
Nios II gen2 is offered in 2 different configurations: Nios II/f (fast), and Nios II/e (economy).
</p>
<h3>Nios II/f</h3>
<p>The Nios II/f core is designed for maximum performance at the expense of core size. Features of Nios II/f include:
</p>
<ul><li>Separate instruction and data caches (512 <a href="/facts/Byte/BNHUp9Qq">B</a> to 64 <a href="/facts/Kilobyte/jIe6t4yv">KB</a>)</li>
<li>Optional <a href="/facts/Memory_management_unit/tJQtAQzI">MMU</a> or <a href="/facts/Memory_protection_unit/mqavTllK">MPU</a></li>
<li>Access to up to 2 <a href="/facts/Gigabyte/s2hb2SEg">GB</a> of external address space</li>
<li>Optional tightly coupled memory for instructions and data</li>
<li>Six-stage pipeline to achieve maximum <a href="/facts/DMIPS/7obFPy8m">DMIPS</a>/MHz</li>
<li>Single-cycle hardware multiply and barrel shifter</li>
<li>Optional hardware divide option</li>
<li>Dynamic <a href="/facts/Branch_predictor/pGPhFMj5">branch prediction</a></li>
<li>Up to 256 custom instructions and unlimited hardware accelerators</li>
<li><a href="/facts/JTAG/IxRc5rG7">JTAG</a> debug module</li>
<li>Optional JTAG debug module enhancements, including hardware breakpoints, data triggers, and real-time trace</li></ul>
<h3>Nios II/s</h3>
<p>Nios II/s core is designed to maintain a balance between performance and cost. This core implementation is not longer supported for Altera Quartus II v.17 and newer. Features of Nios II/s include:
</p>
<ul><li>Instruction cache</li>
<li>Up to 2 GB of external address space</li>
<li>Optional tightly coupled memory for instructions</li>
<li>Five-stage pipeline</li>
<li>Static branch prediction</li>
<li>Hardware multiply, divide, and shift options</li>
<li>Up to 256 custom instructions</li>
<li><a href="/facts/JTAG/IxRc5rG7">JTAG</a> debug module</li>
<li>Optional JTAG debug module enhancements, including hardware breakpoints, data triggers, and real-time trace</li></ul>
<h3>Nios II/e</h3>
<p>The Nios II/e core is designed for smallest possible logic utilization of FPGAs. This is especially efficient for low-cost Cyclone II FPGA applications. Features of Nios II/e include:
</p>
<ul><li>Up to 2 GB of external address space</li>
<li><a href="/facts/JTAG/IxRc5rG7">JTAG</a> debug module</li>
<li>Complete systems in fewer than 700 <a href="/facts/Logic_block/r4RL7uys">LEs</a></li>
<li>Optional debug enhancements</li>
<li>Up to 256 custom instructions</li>
<li>Free, no license required</li></ul>
<h2 id="avalon-switch-fabric-interface">Avalon switch fabric interface</h2>
<p>
Nios II uses the Avalon <a href="/facts/Switched_fabric/TwfTsu3e">switch fabric</a> as the interface to its embedded peripherals. Compared to a traditional bus in a processor-based system, which lets only one bus master access the bus at a time, the Avalon switch fabric, using a slave-side arbitration scheme, lets multiple masters operate simultaneously.
</p>
<h2 id="development-processes">Development processes</h2>
<p>Development for Nios II consists of two separate steps: hardware generation and software creation.
</p><p>Development is hosted inside an Altera application called the Embedded Design Suite (EDS). The EDS contains a complete integrated development environment to manage both hardware and software in two separate steps:
</p>
<h3>Hardware generation process</h3>
<p>Nios II hardware designers use the Qsys system integration tool, a component of the Quartus-II package, to configure and generate a Nios system. The configuration <a href="/facts/Graphical_user_interface/wBlQFWDP">graphical user interface</a> (GUI) allows users to choose the Nios-II's feature-set, and to add peripheral and I/O-blocks (timers, memory-controllers, serial interface, etc.) to the embedded system. When the hardware specification is complete, Quartus-II performs the synthesis, place & route to implement the entire system on the selected FPGA target.
Qsys is replacing the older SOPC (System-on-a-Programmable-Chip) Builder, which could also be used to build a Nios II system, and is being recommended for new projects.<a class="footnote-ref" id="fnref:3" href="#fn:3"><sup>3</sup></a>
</p>
<h3>Software creation process</h3>
<p>A separate package, called the Embedded Design Suite (EDS), manages the software development. Based on the <a href="/facts/Eclipse_(software)/YoqHVjas">Eclipse</a> IDE, the EDS includes a C/C++ compiler (based on the <a href="/facts/GNU_toolchain/8BfT9wfD">GNU toolchain</a>), debugger, and an instruction-set simulator. EDS allows programmers to test their application in simulation, or download and run their compiled application on the actual FPGA host.
</p><p>Because the C/C++ development-chain is based on <a href="/facts/GNU_Compiler_Collection/t07jh01k">GCC</a>, the vast majority of <a href="/facts/Open-source_software/HzTaB8E9">open source</a> software for <a href="/facts/Linux/9FvCKSTq">Linux</a> compiles and runs with minimal or no modification. Third-party operating-systems have also been ported to Nios II. These include Micrium <a href="/facts/MicroC%2fOS-II/TN1GA7II">MicroC/OS-II</a>, <a href="/facts/ECos/oegwUbDy">eCos</a>, <a href="/facts/Segger_Microcontroller_Systems/eN3XeU5c">Segger Microcontroller</a> embOS, <a href="/facts/ChibiOS%2fRT/4z1NFTNo">ChibiOS/RT</a>, <a href="/facts/%25CE%259CCLinux/jSjp2fEF">μCLinux</a> and <a href="/facts/FreeRTOS/v9how6mE">FreeRTOS</a>.
</p><p>GCC 15 removed support for Nios II processors due to Nios II's discontinuation.<a class="footnote-ref" id="fnref:4" href="#fn:4"><sup>4</sup></a>
</p>
<h3>Licensing</h3>
<p>Nios II is comparable to <a href="/facts/MicroBlaze/M0LotP1F">MicroBlaze</a>, a competing <a href="/facts/Soft_microprocessor/pCmb601M">softcore CPU</a> for the <a href="/facts/Xilinx/rbXfxqqG">Xilinx</a> family of FPGA. Unlike MicroBlaze, Nios II is licensable for standard-cell <a href="/facts/Application-specific_integrated_circuit/YGUXpX50">ASICs</a> through a third-party IP provider, <a href="/facts/Synopsys/Szv1V36J">Synopsys</a> Designware. Through the Designware license, designers can port Nios-based designs from an FPGA-platform to a mass production ASIC-device.
</p>
<h2 id="see-also">See also</h2>
<ul><li><a href="/facts/LatticeMico8/1KuDyqVM">LatticeMico8</a></li>
<li><a href="/facts/LatticeMico32/5KXwoTol">LatticeMico32</a></li>
<li><a href="/facts/MicroBlaze/M0LotP1F">MicroBlaze</a></li>
<li><a href="/facts/PicoBlaze/SW3fCRxD">PicoBlaze</a></li>
<li>Micon P200</li></ul>

<h2 id="external-links">External links</h2>
<ul><li><a href="https://www.intel.com/content/www/us/en/products/details/fpga/nios-processor/ii.html">Intel's site about Nios II</a></li>
<li><a href="https://community.intel.com/t5/Nios-V-II-Embedded-Design-Suite/bd-p/nios-II-embedded-design-suite">Nios II Embedded Design Suite forum</a></li>
<li><a href="https://web.archive.org/web/20090121133048/http://nioswiki.com/">Nios community wiki</a></li>
<li><a href="/facts/RTEMS/uULEVKeV">RTEMS</a> real-time operating system</li>
<li><a href="http://instruct1.cit.cornell.edu/courses/ece576/">Cornell ECE576 Microcontroller course using NiosII</a></li>
<li><a href="http://www.freertos.org/FreeRTOS-Nios2.html">FreeRTOS demo documentation for NiosII</a></li>
<li><a href="https://sites.google.com/site/ece31289upb/practicas-de-clase/practica-5-nios-ii">UPB ECE31289 course using Nios II</a></li></ul>

<h2 id="references">References</h2>

<ol>
<li id="fn:1"><p>Altera. "Nios II Embedded Processor Backgrounder" (PDF). <a href="https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/pr/nios2_backgrounder.pdf" target="_blank">https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/pr/nios2_backgrounder.pdf</a> <a href="#fnref:1" class="footnote-back-ref">↩</a></p></li>
<li id="fn:2"><p>"Intel is discontinuing IP ordering codes listed in PDN2312 for Nios® II IP". Intel. Retrieved 2025-01-22. <a href="https://www.intel.com/content/www/us/en/content-details/781327/intel-is-discontinuing-ip-ordering-codes-listed-in-pdn2312-for-nios-ii-ip.html" target="_blank">https://www.intel.com/content/www/us/en/content-details/781327/intel-is-discontinuing-ip-ordering-codes-listed-in-pdn2312-for-nios-ii-ip.html</a> <a href="#fnref:2" class="footnote-back-ref">↩</a></p></li>
<li id="fn:3"><p>"5 Reasons to Switch from SOPC Builder to Qsys". Altera. Retrieved 16 March 2012. <a href="http://www.altera.com/education/webcasts/all/wc-2011-reasons-switch-qsys.html" target="_blank">http://www.altera.com/education/webcasts/all/wc-2011-reasons-switch-qsys.html</a> <a href="#fnref:3" class="footnote-back-ref">↩</a></p></li>
<li id="fn:4"><p>"GCC 15 Ends Support For Altera Nios II Embedded Processors". www.phoronix.com. Retrieved 2025-01-22. <a href="https://www.phoronix.com/news/GCC-15-Drops-Altera-Nios-II" target="_blank">https://www.phoronix.com/news/GCC-15-Drops-Altera-Nios-II</a> <a href="#fnref:4" class="footnote-back-ref">↩</a></p></li>
</ol>

Nios II open-in-new

Nios II