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Delay calculation
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<h2 id="delay-calculation-in-digital-design">Delay calculation in digital design</h2> <p>In the context of semi-custom digital design, pre-characterized digital information is often abstracted in the form of the above-mentioned 2-D look-up table (LUT). The idea behind the semi-custom design method is to use blocks of pre-built and tested components to build something larger, say, a chip. </p><p>In this context, the blocks are <a href="/facts/Logic_gate/RHLulvKI">logic gates</a> such as NAND, OR, AND, etc. Although, in reality, these gates will be composed of transistors, a semi-custom engineer will only be aware of the delay information from the input pin to the output pin, called a timing arc. The 2D table represents the variability of the gate's delay concerning the two independent variables, usually the rate of change of the signal at the input and the load at the output pin. These two variables are called slew and load in design parlance. </p><p>A <a href="/facts/Static_timing_analysis/hhxLf12R">static timing analysis</a> engine will first calculate the delay of the individual cells and string them together to do further analysis. </p> <h2 id="statistical-delay-calculation">Statistical delay calculation</h2> <p class="note">See also: <a href="/facts/Statistical_static_timing_analysis/YIb76Hjy">Statistical static timing analysis</a></p> <p>As chip dimensions get smaller, the delays of both gates and wires may need to be treated as statistical estimates instead of deterministic quantities. For gates, this requires extensions to the library formats. For wires, this requires methods that can calculate the means and distributions of wire delays. In both cases, it is critical to capture the dependence on the underlying variables, such as threshold voltage and metal thickness, since these result in correlations among the delays of nearby components. See <a class="footnote-ref" id="fnref:9" href="#fn:9"><sup>9</sup></a> for an early example. </p> <h2 id="see-also">See also</h2> <ul><li><a href="/facts/Logical_effort/oCdxLxQp">Logical effort</a></li> <li><a href="/facts/Propagation_delay/tUcrAwwe">Propagation delay</a></li> <li><a href="/facts/Electronic_design_automation/o4la3fmX">Electronic design automation</a></li> <li><a href="/facts/Integrated_circuit_design/sE0qVzyo">Integrated circuit design</a></li> <li><a href="/facts/Static_timing_analysis/hhxLf12R">Static timing analysis</a></li> <li><a href="/facts/Statistical_static_timing_analysis/YIb76Hjy">Statistical static timing analysis</a></li> <li><a href="/facts/Standard_Parasitic_Exchange_Format/ToE7nynN">Standard Parasitic Exchange Format</a></li></ul> <h2 id="references">References</h2> <ol> <li id="fn:1"><p>E.-Y. Chung, B.-H. Joo, Y.-K. Lee, K.-H. Kim and S.-H. Lee, “Advanced delay analysis method for submicron ASIC technology,” in Proc. IEEE 5th Int. ASIC Conf. 1992, pp. 471-474. <a href="https://ieeexplore.ieee.org/document/270245/" target="_blank">https://ieeexplore.ieee.org/document/270245/</a> <a href="#fnref:1" class="footnote-back-ref">↩</a></p></li> <li id="fn:2"><p>"Liberty file format, lecture slides" (PDF). Retrieved 15 December 2022. <a href="https://redirect.cs.umbc.edu/~cpatel2/links/641/slides/lect05_LIB.pdf" target="_blank">https://redirect.cs.umbc.edu/~cpatel2/links/641/slides/lect05_LIB.pdf</a> <a href="#fnref:2" class="footnote-back-ref">↩</a></p></li> <li id="fn:3"><p>"Liberty user guide and reference manual" (PDF). Archived from the original (PDF) on 2022-12-15. Retrieved 15 December 2022. <a href="https://web.archive.org/web/20221215133512/https://media.c3d2.de/mgoblin_media/media_entries/659/Liberty_User_Guides_and_Reference_Manual_Suite_Version_2017.06.pdf" target="_blank">https://web.archive.org/web/20221215133512/https://media.c3d2.de/mgoblin_media/media_entries/659/Liberty_User_Guides_and_Reference_Manual_Suite_Version_2017.06.pdf</a> <a href="#fnref:3" class="footnote-back-ref">↩</a></p></li> <li id="fn:4"><p>IEEE standard including DCL <a href="https://web.archive.org/web/20040820022717/http://standards.ieee.org/reading/ieee/std_public/description/dasc/1481-1999_desc.html" target="_blank">https://web.archive.org/web/20040820022717/http://standards.ieee.org/reading/ieee/std_public/description/dasc/1481-1999_desc.html</a> <a href="#fnref:4" class="footnote-back-ref">↩</a></p></li> <li id="fn:5"><p>*W. C. Elmore, The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers , Journal of Applied Physics, January 1948, Volume 19, Issue 1, pp. 55-63. <a href="https://doi.org/10.1063%2F1.1697872" target="_blank">https://doi.org/10.1063%2F1.1697872</a> <a href="#fnref:5" class="footnote-back-ref">↩</a></p></li> <li id="fn:6"><p>If each capacitor is replaced by a current source of the same value, and the root grounded, then the DC voltage at each node is numerically equal to the Elmore delay (first time domain moment). This formulation works whether or not the network is tree structured. See the paper on AWE below for more details. <a href="#fnref:6" class="footnote-back-ref">↩</a></p></li> <li id="fn:7"><p>*Pillage, L.T.; Rohrer, R.A., Asymptotic waveform evaluation for timing analysis <a href="https://doi.org/10.1109%2F43.45867" target="_blank">https://doi.org/10.1109%2F43.45867</a> <a href="#fnref:7" class="footnote-back-ref">↩</a></p></li> <li id="fn:8"><p>*Odabasioglu, A.; Celik, M.; Pileggi, L.T., PRIMA: passive reduced-order interconnect macromodeling algorithm , IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 17, Issue 8, Aug. 1998, pp. 645 - 654 <a href="https://doi.org/10.1109%2F43.712097" target="_blank">https://doi.org/10.1109%2F43.712097</a> <a href="#fnref:8" class="footnote-back-ref">↩</a></p></li> <li id="fn:9"><p>Ying Liu; Pileggi, L.T.; Strojwas, A.J., (1999) Model order-reduction of RC(L) interconnect including variational analysis , proceedings of the 36th Design Automation Conference, 21–25 June 1999, pp. 201 - 206 <a href="https://doi.org/10.1109%2FDAC.1999.781312" target="_blank">https://doi.org/10.1109%2FDAC.1999.781312</a> <a href="#fnref:9" class="footnote-back-ref">↩</a></p></li> </ol>