Bus analyzer

<h2 id="bus-and-protocol-exerciser">Bus and protocol exerciser</h2>
<p>For many bus architectures like PCI Express, PCI, SAS, SATA, and USB, engineers also use a "Bus Exerciser" or “Protocol Exerciser”. Such exercisers can emulate partial or full communication stacks which comply with the specific bus communication standard, thus allowing engineers to surgically control and generate bus traffic to test, debug and validate their designs.
</p><p>These devices make it possible to also generate bad bus traffic as well as good so that the device error recovery systems can be tested. They are also often used to verify compliance with the standard to ensure interoperability of devices since they can reproduce known scenarios in a repeatable way.
</p><p>Exercisers are usually used in conjunction with analyzers, so the engineer gets full visibility of the communication data captured on the bus. Some exercisers are designed as stand-alone systems while others are combined into the same systems used for analysis.
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<h2 id="see-also">See also</h2>
<ul><li><a href="/facts/JTAG/IxRc5rG7">JTAG</a> (boundary scan)</li></ul>

<h2 id="references">References</h2>

<ol>
<li id="fn:1"><p>The basics of bus analyzers <a href="https://www.testandmeasurementtips.com/the-basics-of-bus-analyzers/" target="_blank">https://www.testandmeasurementtips.com/the-basics-of-bus-analyzers/</a> <a href="#fnref:1" class="footnote-back-ref">↩</a></p></li>
<li id="fn:2"><p>In such a case, it is also sometimes referred to as 'digital bus logger'. This is a kind if data logger that implements a sampling mechanism and a filtering mechanism to extract the traffic that relates to a specific or user-defined protocol. See for example this digital data logger <a href="/wiki/Data_logger" target="_blank">/wiki/Data_logger</a> <a href="#fnref:2" class="footnote-back-ref">↩</a></p></li>
</ol>

Bus analyzer open-in-new

Bus analyzer