Verilog-AMS

<h2 id="overview">Overview</h2>
<p>The Verilog-AMS standard was created with the intent of enabling designers of analog and mixed signal systems and integrated circuits to create and use modules that encapsulate high-level behavioral descriptions as well as structural descriptions of systems and components.<a class="footnote-ref" id="fnref:2" href="#fn:2"><sup>2</sup></a><a class="footnote-ref" id="fnref:3" href="#fn:3"><sup>3</sup></a><a class="footnote-ref" id="fnref:4" href="#fn:4"><sup>4</sup></a>
</p><p>Verilog-AMS is an industry standard modeling language for mixed signal circuits. It provides both continuous-time and event-driven modeling semantics, and so is suitable for analog, digital, and mixed analog/digital circuits. It is particularly well suited for verification of very complex analog, mixed-signal and RF integrated circuits.<a class="footnote-ref" id="fnref:5" href="#fn:5"><sup>5</sup></a>
</p><p>Verilog and Verilog/AMS are not procedural programming languages, but event-based <a href="/facts/Hardware_description_language/g19KvKCu">hardware description languages</a> (HDLs). As such, they provide sophisticated and powerful language features for definition and synchronization of parallel actions and events. On the other hand, many actions defined in HDL program statements can run in parallel (somewhat similar to threads and tasklets in procedural languages, but much more fine-grained). However, Verilog/AMS can be coupled with procedural languages like the ANSI C language using the <a href="/facts/Verilog_Procedural_Interface/z4vQW3fC">Verilog Procedural Interface</a> of the simulator, which eases testsuite implementation, and allows interaction with legacy code or testbench equipment.
</p><p>The original intention of the Verilog-AMS committee was a single language for both analog and digital design, however due to delays in the merger process it remains at <a href="/facts/Accellera/PtqWU00v">Accellera</a> while <a href="/facts/Verilog/efVqbKXg">Verilog</a> evolved into <a href="/facts/SystemVerilog/wkBdc179">SystemVerilog</a> and went to the IEEE.
</p>
<h2 id="code-example">Code example</h2>
<p>Verilog/AMS is a superset of the Verilog digital HDL, so all statements in digital domain work as in <a href="/facts/Verilog/efVqbKXg">Verilog</a> (see there for examples). All analog parts work as in <a href="/facts/Verilog-A/oVDzKWEz">Verilog-A</a>.
</p><p>The following code example in Verilog-AMS shows a <a href="/facts/Digital-to-analog_converter/5loEvAeb">DAC</a> which is an example for analog processing which is triggered by a digital signal:
</p>
`include "constants.vams"
`include "disciplines.vams"
// Simple DAC model
module dac_simple(aout, clk, din, vref);
	
	// Parameters
	parameter integer bits = 4 from [1:24];
	parameter integer td = 1n from[0:inf);  // Processing delay of the DAC
	
	// Define input/output
	input clk, vref;
	input [bits-1:0] din;
	output aout;
		
	//Define port types
	logic clk;
	logic [bits-1:0] din;
	electrical  aout, vref;
	
	// Internal variables
	real aout_new, ref;
	integer i;
	
	// Change signal in the analog part
	analog begin
		@(posedge clk) begin // Change output only for rising clock edge	
			
			aout_new = 0;
			ref = V(vref);
			
			for(i=0; i<bits; i=i+1) begin
				ref = ref/2;
				aout_new = aout_new + ref * din[i];
			end
		end	
		V(aout) <+ transition(aout_new, td, 5n); // Get a smoother transition when output level changes
	end
endmodule

<p>The <a href="/facts/Analog-to-digital_converter/8YYNsMFg">ADC</a> model is reading analog signals in the digital blocks:
</p>
`include "constants.vams"
`include "disciplines.vams"
// Simple ADC model
module adc_simple(clk, dout, vref, vin);
	
	// Parameters
	parameter integer bits = 4 from[1:24]; // Number of bits
	parameter integer td = 1 from[0:inf);  // Processing delay of the ADC
	
	// Define input/output
	input clk, vin, vref;
	output [bits-1:0] dout;
	
	//Define port types
	electrical vref, vin;
	logic clk;
	reg [bits-1:0] dout;
	
	// Internal variables	
	real ref, sample;
	integer i;
	
	
	initial begin
		dout = 0;
	end

// Perform sampling in the digital blocks for rising clock edge
	always @(posedge clk) begin
		
		sample = V(vin);
		ref = V(vref);
			
		for(i=0; i<bits; i=i+1) begin
			
			ref = ref/2;
				
			if(sample > ref) begin
				dout[i] <= #(td) 1;
				sample = sample - ref;
			end
			else
				dout[i] <= #(td) 0;
		end
	end
endmodule

<h2 id="implementations">Implementations</h2>
<p>While the language was initially only supported by commercial companies, parts of the behavioural modeling subset, "Verilog-A" was adopted by the transistor-modeling community. The ADMS translator supports it for open-source simulators like Xyce and ngSPICE. A more complete implementation is now available through OpenVAF. The post-SPICE simulator Gnucap was designed in accordance with the standard document, and its support for Verilog-AMS for both the simulator level and the behavioral modeling is growing.
</p>
<h2 id="see-also">See also</h2>
<ul><li><a href="/facts/VHDL-AMS/IRRos9XK">VHDL-AMS</a></li></ul>

<h2 id="external-links">External links</h2>
<ul><li>I. Miller and T. Cassagnes, "Verilog-AMS Eases Mixed Mode Signal Simulation," <i>Technical Proceedings of the 2000 International Conference on Modeling and Simulation of Microsystems</i>, pp. 305–308, Available: <a href="https://web.archive.org/web/20070927051749/http://www.nsti.org/publ/MSM2000/T31.01.pdf">https://web.archive.org/web/20070927051749/http://www.nsti.org/publ/MSM2000/T31.01.pdf</a></li></ul>
<h3>General</h3>
<ul><li><a href="http://www.accellera.org/activities/committees/verilog-ams/">Accellera Verilog Analog Mixed-Signal Group</a></li>
<li><a href="http://www.verilogams.com">verilogams.com</a> — User's manual for Verilog-AMS and Verilog-A</li>
<li><a href="http://www.designers-guide.org/VerilogAMS/">The Designer's Guide Community, Verilog-A/MS</a> — Examples of models written in Verilog-AMS</li>
<li><a href="http://www.eda.org/twiki/bin/view.cgi/VerilogAMS">EDA.ORG AMS Wiki</a> - Issues, future development, SystemVerilog integration</li></ul>
<h3>Open Source Implementations</h3>
<ul><li><a href="http://ovams.sourceforge.net/">OpenVAMS, an Open-Source VerilogAMS-1.3 Parser with internal VPI-like representation</a></li>
<li><a href="http://www.v-ms.com/">V2000 project - Verilog-AMS parser & elaborator</a></li>
<li><a href="https://man.sr.ht/~dspom/openvaf_doc/">OpenVAF Verilog-A compiler</a></li>
<li><a href="https://xyce.sandia.gov/">Xyce</a></li>
<li><a href="http://gnucap.org/dokuwiki/doku.php/gnucap:projects:nlnet:verilogams">Gnucap</a></li></ul>

<h2 id="references">References</h2>

<ol>
<li id="fn:1"><p>Scheduling semantics are specified in the Verilog/AMS Language Reference Manual, section 8. <a href="#fnref:1" class="footnote-back-ref">↩</a></p></li>
<li id="fn:2"><p>Accellera Verilog Analog Mixed-Signal Group, "Overview," http://www.verilog.org/verilog-ams/htmlpages/overview.html <a href="http://www.verilog.org/verilog-ams/htmlpages/overview.html" target="_blank">http://www.verilog.org/verilog-ams/htmlpages/overview.html</a> <a href="#fnref:2" class="footnote-back-ref">↩</a></p></li>
<li id="fn:3"><p>Verilog-AMS Language Reference Manual <a href="https://www.accellera.org/images/downloads/standards/v-ams/VAMS-LRM-2-4.pdf" target="_blank">https://www.accellera.org/images/downloads/standards/v-ams/VAMS-LRM-2-4.pdf</a> <a href="#fnref:3" class="footnote-back-ref">↩</a></p></li>
<li id="fn:4"><p>The Designer's Guide to Verilog-AMS <a href="http://www.designers-guide.org/Books/dg-vams/index.html" target="_blank">http://www.designers-guide.org/Books/dg-vams/index.html</a> <a href="#fnref:4" class="footnote-back-ref">↩</a></p></li>
<li id="fn:5"><p>Verification of Complex Analog Integrated Circuits Archived October 18, 2006, at the Wayback Machine <a href="http://www.designers-guide.com/docs/cicc06-dgc.pdf" target="_blank">http://www.designers-guide.com/docs/cicc06-dgc.pdf</a> <a href="#fnref:5" class="footnote-back-ref">↩</a></p></li>
</ol>

Verilog-AMS open-in-new

Verilog-AMS