Digital timing diagram

<h2 id="diagram-convention">Diagram convention</h2>
<p>Most timing diagrams use the following conventions:
</p>
<ul><li>Higher value is a logic one</li>
<li>Lower value is a logic zero</li>
<li>A slot showing a high and low is an either-or (such as on a data line)</li>
<li>A Z indicates <a href="/facts/High_impedance/DNNoHHvQ">high impedance</a></li>
<li>A greyed out slot is a <a href="/facts/Don%27t-care_(logic)/kvQuwYMK">don't-care</a> or indeterminate.</li></ul>
<h2 id="example-spi-bus-timing">Example: SPI bus timing</h2>

<p>The timing diagram example on the right describes the <a href="/facts/Serial_Peripheral_Interface_Bus/uSCU56eG">Serial Peripheral Interface (SPI) Bus</a>.
Most SPI master nodes can set the clock polarity (CPOL) and clock phase (CPHA) with respect to the data.
This timing diagram shows the clock for both values of CPOL and the values for the two data lines (MISO & MOSI) for each value of CPHA.
Note that when CPHA=1, then the data is delayed by one-half clock cycle.
</p><p>SPI operates in the following way:
</p>
<ul><li>The master determines an appropriate CPOL & CPHA value</li>
<li>The master pulls down the <a href="/facts/Slave_select/Vth2yLfT">slave select</a> (SS) line for a specific slave chip</li>
<li>The master clocks SCK at a specific frequency</li>
<li>During each of the eight clock cycles, the transfer is <a href="/facts/Full_duplex/LCULeVxr">full duplex</a>:
<ul><li>The master writes on the MOSI line and reads the MISO line</li>
<li>The slave writes on the MISO line and reads the MOSI line</li></ul></li>
<li>When finished the master can continue with another <a href="/facts/Byte/BNHUp9Qq">byte</a> transfer or pull SS high to end the transfer</li></ul>
<p>When a slave's SS line is high, both its MISO and MOSI line should be high impedance to avoid disrupting a transfer to a different slave.
Before SS being pulled low, the MISO & MOSI lines are indicated with a "z" for high impedance.
Also, before the SS is pulled low, the "cycle #" row is meaningless and is shown greyed out.
</p><p>Note that for CPHA=1, the MISO & MOSI lines are undefined until after the first clock edge and are also shown greyed out before that.
</p><p>A more typical timing diagram has just a single clock and numerous data lines.
</p>
<h2 id="software">Software</h2>
<p>The following diagram software may be used to draw timing diagrams:
</p>
<ul><li><a href="/facts/PlantUML/JXGzHnK3">PlantUML</a><a class="footnote-ref" id="fnref:2" href="#fn:2"><sup>2</sup></a></li>
<li>Timing Diagrammer<a class="footnote-ref" id="fnref:3" href="#fn:3"><sup>3</sup></a></li></ul>

<h2 id="external-links">External links</h2>

Wikimedia Commons has media related to Digital timing diagrams.

<ul><li><a href="http://wavedrom.com">Wavedrom</a> is an online timing diagram editor.</li>
<li><a href="https://github.com/hacksterous/TimingDiagrammer">Timing Diagrammer</a> has a Windows binary.</li></ul>

<h2 id="references">References</h2>

<ol>
<li id="fn:1"><p>"Timing Diagram". PlantUML. 2024. Archived from the original on 11 December 2024. Retrieved 10 February 2023. <a href="https://plantuml.com/timing-diagram" target="_blank">https://plantuml.com/timing-diagram</a> <a href="#fnref:1" class="footnote-back-ref">↩</a></p></li>
<li id="fn:2"><p>"Timing Diagram". PlantUML. 2024. Archived from the original on 11 December 2024. Retrieved 10 February 2023. <a href="https://plantuml.com/timing-diagram" target="_blank">https://plantuml.com/timing-diagram</a> <a href="#fnref:2" class="footnote-back-ref">↩</a></p></li>
<li id="fn:3"><p>"TimingDiagrammer". GitHub. Archived from the original on 21 January 2023. Retrieved 10 February 2023. <a href="https://github.com/hacksterous/TimingDiagrammer" target="_blank">https://github.com/hacksterous/TimingDiagrammer</a> <a href="#fnref:3" class="footnote-back-ref">↩</a></p></li>
</ol>

Digital timing diagram open-in-new

Digital timing diagram