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<h2 id="finite-state-machine-with-data-path">Finite-state machine with data path</h2> <p>A finite-state machine with data path (FSMD) is a mathematical abstraction which combines a <a href="/facts/Finite-state_machine/GMusWd0a">finite-state machine</a>, which controls the <a href="/facts/Program_flow/2XTDfErC">program flow</a>, with a data path. It can be used to design <a href="/facts/Digital_logic/RHLulvKI">digital logic</a> or <a href="/facts/Computer_program/e38jH9N9">computer programs</a>.<a class="footnote-ref" id="fnref:6" href="#fn:6"><sup>6</sup></a><a class="footnote-ref" id="fnref:7" href="#fn:7"><sup>7</sup></a> </p><p>FSMDs are essentially sequential programs in which statements have been scheduled into states, thus resulting in more complex state diagrams. Here, a program is converted into a complex state diagram in which states and arcs may include <a href="/facts/Arithmetic_expression/MPrMlYbE">arithmetic expressions</a>, and those expressions may use external inputs and outputs as well as variables. The FSMD level of abstraction is often referred to as the <a href="/facts/Register-transfer_level/SDA3ET30">register-transfer level</a>. </p><p>FSMs do not use variables or arithmetic operations/conditions, thus FSMDs are more powerful than FSMs. An FSMD is equivalent to a <a href="/facts/Turing_machine/ojCtglYu">Turing machine</a> in expressiveness. </p> <h2 id="references">References</h2> <ol> <li id="fn:1"><p>Null, Linda; Lobur, Julia (2006). The Essentials of Computer Organization and Architecture. Jones & Bartlett Learning. p. 2016. ISBN 978-0-7637-3769-6. All computers have a CPU that can be divided into two pieces. The first is the datapath, which is a network of storage units (registers) and arithmetic and logic units... connected by buses... where the timing is controlled by clocks. <a href="978-0-7637-3769-6" target="_blank">978-0-7637-3769-6</a> <a href="#fnref:1" class="footnote-back-ref">↩</a></p></li> <li id="fn:2"><p>Null, Linda; Lobur, Julia (2006). The Essentials of Computer Organization and Architecture. Jones & Bartlett Learning. p. 2016. ISBN 978-0-7637-3769-6. All computers have a CPU that can be divided into two pieces. The first is the datapath, which is a network of storage units (registers) and arithmetic and logic units... connected by buses... where the timing is controlled by clocks. <a href="978-0-7637-3769-6" target="_blank">978-0-7637-3769-6</a> <a href="#fnref:2" class="footnote-back-ref">↩</a></p></li> <li id="fn:3"><p>Edward Bosworth. "Overview of Computer Architecture". <a href="http://www.edwardbosworth.com/My5155_Slides/Chapter09/ComputerArchitectureOverview.htm" target="_blank">http://www.edwardbosworth.com/My5155_Slides/Chapter09/ComputerArchitectureOverview.htm</a> <a href="#fnref:3" class="footnote-back-ref">↩</a></p></li> <li id="fn:4"><p>Edward Bosworth. "CPU Bus Structure". <a href="http://www.edwardbosworth.com/My5155_Slides/Chapter11/CPUBusStructure.htm" target="_blank">http://www.edwardbosworth.com/My5155_Slides/Chapter11/CPUBusStructure.htm</a> <a href="#fnref:4" class="footnote-back-ref">↩</a></p></li> <li id="fn:5"><p>J. R. Hauser and J. Wawrzynek, Garp: a MIPS processor with a reconfigurable coprocessor, FCCM’97, 1997, pp. 12–21. Archived 2017-09-22 at the Wayback Machine <a href="http://class.ece.iastate.edu/tyagi/cpre583/documents/garp.pdf" target="_blank">http://class.ece.iastate.edu/tyagi/cpre583/documents/garp.pdf</a> <a href="#fnref:5" class="footnote-back-ref">↩</a></p></li> <li id="fn:6"><p>Zhu, Jianwen; Gajski, Daniel D. (1999-03-01). "A unified formal model of ISA and FSMD". Proceedings of the seventh international workshop on Hardware/Software codesign - CODES '99. New York, NY, USA: Association for Computing Machinery. pp. 121–125. doi:10.1145/301177.301504. ISBN 978-1-58113-132-1. S2CID 5426988. <a href="978-1-58113-132-1" target="_blank">978-1-58113-132-1</a> <a href="#fnref:6" class="footnote-back-ref">↩</a></p></li> <li id="fn:7"><p>Hsu, Y.C.; Liu, T.Y.; Tsai, F.S.; Lin, S.Z.; Yu, C. (1994-12-05). "Digital design from concept to prototype in hours". Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems. pp. 175–181. doi:10.1109/APCCAS.1994.514545. ISBN 0-7803-2440-4. S2CID 61056791. <a href="0-7803-2440-4" target="_blank">0-7803-2440-4</a> <a href="#fnref:7" class="footnote-back-ref">↩</a></p></li> </ol>