Multi-threshold CMOS

<h2 id="implementation">Implementation</h2>

The most common implementation of MTCMOS for reducing <a href="/facts/Electric_power/w61ID9yQ">power</a> makes use of sleep transistors. Logic is supplied by a virtual <a href="/facts/Power_supply_rail/3nvssXFG">power rail</a>. Low Vth devices are used in the logic where fast switching speed is important. High Vth devices connecting the power rails and virtual power rails are turned on in active mode, off in <a href="/facts/Sleep_mode/lj6HSbyU">sleep mode</a>. High Vth devices are used as sleep transistors to reduce static leakage power.
The design of the power <a href="/facts/Switch/vqbNDgYm">switch</a> which turns on and off the <a href="/facts/Power_supply/4A8zBRHn">power supply</a> to the <a href="/facts/Logic_gate/RHLulvKI">logic gates</a> is essential to low-voltage, high-speed <a href="/facts/Electrical_network/zt94kTW0">circuit</a> techniques such as MTCMOS. The speed, area, and power of a logic circuit are influenced by the characteristics of the power switch. 
In a "coarse-grained" approach, high Vth sleep transistors gate the power to entire logic blocks.<a class="footnote-ref" id="fnref:3" href="#fn:3">3</a> The sleep signal is de-asserted during active mode, causing the transistor to turn on and provide virtual power (ground) to the low Vth logic. The sleep signal is asserted during <a href="/facts/Sleep_mode/lj6HSbyU">sleep mode</a>, causing the transistor to turn off and disconnect power (ground) from the low Vth logic. The drawbacks of this approach are that:

<ul><li>logic blocks must be partitioned to determine when a block may be safely turned off (on)</li>
<li>sleep transistors are large and must be carefully sized to supply the current required by the circuit block</li>
<li>an always active (never in sleep mode) power management circuit must be added</li></ul>
In a "fine-grained" approach, high Vth sleep transistors are incorporated within every gate. Low Vth transistors are used for the pull-up and pull-down networks, and a high Vth transistor is used to gate the leakage current between the two networks. This approach eliminates problems of logic block partitioning and sleep transistor sizing. However, a large amount of area overhead is added due both to inclusion of additional transistors in every <a href="/facts/Boolean_algebra/VkCToAmg">Boolean</a> gate, and in creating a sleep signal distribution tree. 
An intermediate approach is to incorporate high Vth sleep transistors into threshold gates having more complicated function. Since fewer such threshold gates are required to implement any arbitrary function compared to Boolean gates, incorporating MTCMOS into each gate requires less area overhead. Examples of threshold gates having more complicated function are found with <a href="/facts/Null_Convention_Logic/n4ah2j7H">Null Convention Logic</a> (NCL)<a class="footnote-ref" id="fnref:4" href="#fn:4">4</a> and <a href="/facts/Sleep_Convention_Logic/n4ah2j7H">Sleep Convention Logic</a> (SCL).<a class="footnote-ref" id="fnref:5" href="#fn:5">5</a><a class="footnote-ref" id="fnref:6" href="#fn:6">6</a> Some art is required to implement MTCMOS without causing glitches or other problems.

<h2 id="references">References</h2>

<ol>
<li id="fn:1">Anis, Mohab; Areibi, Shawki; Mahmoud, Mohamed; Elmasry, Mohamed (2002-06-10). Written at Ontario, Canada. "Dynamic and Leakage Power Reduction in MTCMOS Circuits Using an Automated Efficient Gate Clustering Technique". Design Automation Conference. Proceedings. 39. New Orleans, Louisiana, USA: 480–485. CiteSeerX 10.1.1.11.9193. ISBN 1-58113-461-4. Archived from the original on 2023-05-18. Retrieved 2023-05-18. <a href="1-58113-461-4" target="_blank">1-58113-461-4</a> <a href="#fnref:1" class="footnote-back-ref">↩</a></li>
<li id="fn:2">Oklobdzija, Vojin G. (1997). Digital Design and Fabrication. CRC Press. pp. 12–18. ISBN 978-0-8493-8602-2. <a href="978-0-8493-8602-2" target="_blank">978-0-8493-8602-2</a> <a href="#fnref:2" class="footnote-back-ref">↩</a></li>
<li id="fn:3">Smith, Scott; Di, Jia (2009). Designing Asynchronous Circuits using NULL Conventional Logic (NCL). Morgan & Claypool Publishers [d]. pp. 61–73. ISBN 978-1-59829-981-6. <a href="978-1-59829-981-6" target="_blank">978-1-59829-981-6</a> <a href="#fnref:3" class="footnote-back-ref">↩</a></li>
<li id="fn:4">Fant, Karl M. (2005). Logically determined design: clockless system design with NULL convention logic (NCL). Chichester, UK: John Wiley and Sons. ISBN 978-0-471-68478-7. <a href="978-0-471-68478-7" target="_blank">978-0-471-68478-7</a> <a href="#fnref:4" class="footnote-back-ref">↩</a></li>
<li id="fn:5">Smith, Scott; Di, Jia (2009). Designing Asynchronous Circuits using NULL Conventional Logic (NCL). Morgan & Claypool Publishers [d]. pp. 61–73. ISBN 978-1-59829-981-6. <a href="978-1-59829-981-6" target="_blank">978-1-59829-981-6</a> <a href="#fnref:5" class="footnote-back-ref">↩</a></li>
<li id="fn:6">Smith, Scott; Di, Jia. "U.S. 7,977,972 Ultra-Low Power Multi-threshold Asychronous Circuit Design". Retrieved 2011-12-12. <a href="http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=7977972.PN.&OS=PN/7977972&RS=PN/7977972" target="_blank">http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=7977972.PN.&OS=PN/7977972&RS=PN/7977972</a> <a href="#fnref:6" class="footnote-back-ref">↩</a></li>
</ol>

Multi-threshold CMOS open-in-new

Multi-threshold CMOS