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Bus functional model
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<h2 id="transaction-verification-models">Transaction verification models</h2> <p>BFMs are sometimes referred to as TVMs or Transaction Verification Models. This is to emphasize that bus operations of the model have been bundled into atomic bus transactions to make it easier to issue and view bus transactions. Visualizations of the bus transactions modeled by TVMs are similar to the output of a <a href="/facts/Bus_analyzer/tS21m4Qh">protocol analyzer</a> or bus sniffer. </p> <ul><li>Mitchel, Donna (2001). <a href="https://web.archive.org/web/20040122033338/http://www.omimo.be/Magazine/01q2/2001q2_p027.pdf">"Manual and Automatic VHDL/Verilog Test Bench Coding Techniques"</a> (PDF). <i>Dedicated Systems Magazine</i>. 9 (2). Archived from <a href="http://www.omimo.be/Magazine/01q2/2001q2_p027.pdf">the original</a> (PDF) on 22 January 2004. Retrieved 8 April 2013.</li></ul>