MyHDL

<h2 id="conversion-examples">Conversion examples</h2>
Here, you can see some examples of conversions from MyHDL designs to VHDL and/or Verilog.<a class="footnote-ref" id="fnref:8" href="#fn:8">8</a>
A small combinatorial design
The example is a small combinatorial design, more specifically the binary to Gray code converter:

def bin2gray(B, G, width: int):
 """Gray encoder.

B -- input intbv signal, binary encoded
    G -- output intbv signal, gray encoded
    width -- bit width
    """

@always_comb
    def logic():
        Bext = intbv(0)[width + 1 :]
        Bext[:] = B
        for i in range(width):
            G.next[i] = Bext[i + 1] ^ Bext[i]

return logic

You can create an instance and convert to Verilog and VHDL as follows:

width = 8

B = Signal(intbv(0)[width:])
G = Signal(intbv(0)[width:])

bin2gray_inst = toVerilog(bin2gray, B, G, width)
bin2gray_inst = toVHDL(bin2gray, B, G, width)

The generated Verilog code looks as follows:

module bin2gray (
 B,
 G
);

input [7:0] B;
output [7:0] G;
reg [7:0] G;

always @(B) begin: BIN2GRAY_LOGIC
 integer i;
 reg [9-1:0] Bext;
 Bext = 9'h0;
 Bext = B;
 for (i=0; i<8; i=i+1) begin
 G[i] <= (Bext[(i + 1)] ^ Bext[i]);
 end
end

endmodule

The generated VHDL code looks as follows:

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;

use work.pck_myhdl_06.all;

entity bin2gray is
    port (
        B: in unsigned(7 downto 0);
        G: out unsigned(7 downto 0)
    );
end entity bin2gray;

architecture MyHDL of bin2gray is

begin

BIN2GRAY_LOGIC: process (B) is
 variable Bext: unsigned(8 downto 0);
begin
 Bext := to_unsigned(0, 9);
 Bext := resize(B, 9);
 for i in 0 to 8-1 loop
 G(i) <= (Bext((i + 1)) xor Bext(i));
 end loop;
end process BIN2GRAY_LOGIC;

end architecture MyHDL;

<h2 id="see-also">See also</h2>
<ul><li><a href="/facts/Comparison_of_Free_EDA_software/uCYS0eQY">Comparison of Free EDA software</a></li>
<li><a href="/facts/Comparison_of_EDA_Software/uCYS0eQY">Comparison of EDA Software</a></li>
<li><a href="/facts/Electronic_design_automation/o4la3fmX">Electronic design automation</a> (EDA)</li>
<li><a href="/facts/C_to_HDL/G3yWpNhs">C to HDL</a> compilers</li></ul>

<h2 id="references">References</h2>

<ol>
<li id="fn:1">"Home". myhdl.org. <a href="http://www.myhdl.org/" target="_blank">http://www.myhdl.org/</a> <a href="#fnref:1" class="footnote-back-ref">↩</a></li>
<li id="fn:2">"Conversion to Verilog and VHDL — MyHDL 0.11 documentation". <a href="http://docs.myhdl.org/en/stable/manual/conversion.html" target="_blank">http://docs.myhdl.org/en/stable/manual/conversion.html</a> <a href="#fnref:2" class="footnote-back-ref">↩</a></li>
<li id="fn:3">"What's new in MyHDL 0.6 — MyHDL 0.11 documentation". <a href="http://docs.myhdl.org/en/stable/whatsnew/0.6.html#conversion-of-test-benches" target="_blank">http://docs.myhdl.org/en/stable/whatsnew/0.6.html#conversion-of-test-benches</a> <a href="#fnref:3" class="footnote-back-ref">↩</a></li>
<li id="fn:4">"What's new in MyHDL 0.6 — MyHDL 0.11 documentation". <a href="http://docs.myhdl.org/en/stable/whatsnew/0.6.html#conversion-of-lists-of-signals" target="_blank">http://docs.myhdl.org/en/stable/whatsnew/0.6.html#conversion-of-lists-of-signals</a> <a href="#fnref:4" class="footnote-back-ref">↩</a></li>
<li id="fn:5">"What's new in MyHDL 0.6 — MyHDL 0.11 documentation". <a href="http://docs.myhdl.org/en/stable/whatsnew/0.6.html#conversion-output-verification" target="_blank">http://docs.myhdl.org/en/stable/whatsnew/0.6.html#conversion-output-verification</a> <a href="#fnref:5" class="footnote-back-ref">↩</a></li>
<li id="fn:6">"Co-simulation with Verilog — MyHDL 0.11 documentation". <a href="http://docs.myhdl.org/en/stable/manual/cosimulation.html" target="_blank">http://docs.myhdl.org/en/stable/manual/cosimulation.html</a> <a href="#fnref:6" class="footnote-back-ref">↩</a></li>
<li id="fn:7">"MyHDL: A Python-Based Hardware Description Language | Linux Journal". <a href="http://www.linuxjournal.com/article/7542" target="_blank">http://www.linuxjournal.com/article/7542</a> <a href="#fnref:7" class="footnote-back-ref">↩</a></li>
<li id="fn:8">"Conversion examples — MyHDL 0.11 documentation". <a href="http://docs.myhdl.org/en/stable/manual/conversion_examples.html" target="_blank">http://docs.myhdl.org/en/stable/manual/conversion_examples.html</a> <a href="#fnref:8" class="footnote-back-ref">↩</a></li>
</ol>

MyHDL open-in-new

MyHDL