Menu
Home
People
Places
Arts
History
Plants & Animals
Science
Life & Culture
Technology
Reference.org
List of VIA microprocessor cores
open-in-new
<h2 id="cyrixdesign-cyrix-iii"><a href="/facts/Cyrix/zPI6NhTm">Cyrix</a> design (<a href="/facts/Cyrix_III/v3PtdAEq">Cyrix III</a>)</h2> <ul><li>All models<a class="footnote-ref" id="fnref:1" href="#fn:1"><sup>1</sup></a> support: <i><a href="/facts/MMX_(instruction_set)/8o3JJhns">MMX</a>, <a href="/facts/3DNow!/QYJL2HBt">3DNow!</a></i></li></ul> <table><tbody><tr><th>Marketingname</th><th>Core</th><th>Frequency</th><th><a href="/facts/Front-side_bus/LgYSB7Wl">Front-side bus</a></th><th><a href="/facts/CPU_cache/x8BYFcdv">L1-cache</a></th><th>L2-cache</th><th><a href="/facts/Floating_point_unit/XWTW2AbF">FPU</a>speed</th><th>Pipelinestages</th><th>Typical power</th><th>Voltage</th><th>Process</th></tr><tr><td>Cyrix III</td><td>Joshua</td><td>350-450 MHz</td><td>100-133 MHz</td><td>64 <a href="/facts/Kilobyte/jIe6t4yv">KB</a></td><td>256 KB</td><td>100%</td><td>?</td><td>13-16 W</td><td>2.2 V</td><td>180 nm Al</td></tr></tbody></table> <h2 id="centaur-technologydesign"><a href="/facts/Centaur_Technology/blY0qw55">Centaur Technology</a> design</h2> <h3><a href="/facts/Cyrix_III/v3PtdAEq">Cyrix III</a>, <a href="/facts/VIA_C3/Y4IQ8VCd">C3</a></h3> <ul><li>All models<a class="footnote-ref" id="fnref:2" href="#fn:2"><sup>2</sup></a> support: <i><a href="/facts/MMX_(instruction_set)/8o3JJhns">MMX</a>, <a href="/facts/3DNow!/QYJL2HBt">3DNow!</a></i></li></ul> <table><tbody><tr><th>Marketingname</th><th>Core</th><th>Frequency</th><th>Front-side bus</th><th>L1 cache</th><th>L2 cache</th><th>FPUspeed</th><th>Pipelinestages</th><th>Typical power</th><th>Voltage</th><th>Process</th></tr><tr><td>Cyrix III, C3, 1Giga<i>Pro</i></td><td>Samuel (C5A)</td><td>466-733 MHz</td><td>100-133 MHz</td><td>128 KB</td><td>0 KB</td><td>50%</td><td>12</td><td>6.8-10.6 W</td><td>1.8-2.0 V</td><td>180 nm Al</td></tr><tr><td>Cyrix III, C3, 1Giga<i>Pro</i>, Eden ESP, XP 2000+</td><td>Samuel 2 (C5B)</td><td>600-800 MHz</td><td>100-133 MHz</td><td>128 KB</td><td>64 KB</td><td>50%</td><td>12</td><td>5.8-6.6 W</td><td>1.5-1.65 V</td><td>150 nm Al</td></tr><tr><td>C3, Eden ESP</td><td>Ezra (C5C)</td><td>733-933 MHz</td><td>100-133 MHz</td><td>128 KB</td><td>64 KB</td><td>50%</td><td>12</td><td>5.3-5.9 W</td><td>1.35 V</td><td>130 nm Al</td></tr><tr><td>C3</td><td>Ezra-T (C5N)</td><td>800-1000 MHz</td><td>100-133 MHz</td><td>128 KB</td><td>64 KB</td><td>50%</td><td>12</td><td>5.3-11.8 W</td><td>1.35-1.45 V</td><td>130 nm Al</td></tr></tbody></table> <h3><a href="/facts/VIA_C3/Y4IQ8VCd">C3</a>, <a href="/facts/VIA_C7/a4nqwGyr">C7</a></h3> <ul><li>All models<a class="footnote-ref" id="fnref:3" href="#fn:3"><sup>3</sup></a> support: <i><a href="/facts/MMX_(instruction_set)/8o3JJhns">MMX</a>, <a href="/facts/Streaming_SIMD_Extensions/mMa6EFyB">SSE</a></i></li> <li><a href="/facts/SSE2/cheNDPSK">SSE2</a>, <a href="/facts/SSE3/Ch9oP4oh">SSE3</a>, <a href="/facts/NX_bit/MnBB93BK">NX bit</a> supported by Esther (C5J)</li> <li><a href="/facts/X86/Kypq5fgu">x86</a> (no <a href="/facts/X86-64/cyWvUFlP">x86-64</a>)</li></ul> <table><tbody><tr><th>Marketingname</th><th>Core</th><th>Frequency</th><th>Front-side bus</th><th>L1 cache</th><th>L2 cache</th><th>FPUspeed</th><th>Pipelinestages</th><th>Typical power</th><th>Voltage</th><th>Process</th></tr><tr><td>C3, Eden ESP, Eden-N</td><td>Nehemiah (C5XL)</td><td>800-1400 MHz</td><td>133 MHz</td><td>128 KB</td><td>64 KB</td><td>100%</td><td>16</td><td>15-19 W</td><td>1.25 or 1.4-1.45 V</td><td>130 nm Cu</td></tr><tr><td>C3</td><td>Nehemiah+ (C5P)</td><td>1-1.4 GHz</td><td>133 MHz</td><td>128 KB</td><td>64 KB</td><td>100%</td><td>16</td><td>11-12 W</td><td>1.25 V</td><td>130 nm Cu</td></tr><tr><td>C7, C7-D, C7-M, Eden, Eden ULV</td><td>Esther (C5J)</td><td>0.4-2.0 GHz</td><td>400-533 MT/s</td><td>128 KB</td><td>128 KB</td><td>100%</td><td>16</td><td>12-20 W</td><td>0.9-1.1(?) V</td><td>90 nm SOI</td></tr></tbody></table> <table><tbody><tr><th>Series</th><th>Model</th><th>Core</th><th>Frequency[MHz]</th><th><a href="/facts/Front-side_bus/LgYSB7Wl">Front-side bus</a>[MHz]</th><th>Year</th><th>Process[nm]</th><th>Package size[mm2]</th><th>Power[W]</th><th>L2 cache[K]</th><th>L1 I/D cache[K]</th><th>Performance[SPEC2000]</th></tr><tr><th rowspan="5"><a href="/facts/VIA_Eden/FI5wu2wE">Eden</a></th><td>Eden ESP</td><td>Samuel 2</td><td>300–600</td><td>66/100/133</td><td>2001</td><td>150</td><td>35×35</td><td>2.5–6</td><td>64</td><td>64/64</td><td>Unknown</td></tr><tr><td>Eden ESP</td><td>Nehemiah</td><td>667–1000</td><td>133/200</td><td>2003–2004</td><td>130</td><td>35×35</td><td>6–7</td><td>64</td><td>64/64</td><td>Unknown</td></tr><tr><td>Eden-N</td><td>Nehemiah</td><td>533–1000</td><td>133</td><td>2003</td><td>130</td><td>15×15</td><td>2.5–7</td><td>64</td><td>64/64</td><td>Unknown</td></tr><tr><td>Eden</td><td>Esther</td><td>400–1500</td><td>400–800</td><td>2006–2007</td><td>90</td><td>30</td><td><7.5</td><td>128</td><td>32/32</td><td>Unknown</td></tr><tr><td>Eden X2</td><td>Unknown</td><td>800</td><td>Unknown</td><td>2011</td><td>40</td><td>11×6</td><td>Unknown</td><td>Unknown</td><td>Unknown</td><td>Unknown</td></tr><tr><th rowspan="4"><a href="/facts/VIA_C3/Y4IQ8VCd">C3</a></th><td>C3</td><td>Samuel 2</td><td>667–800</td><td>100–133</td><td>2001</td><td>150</td><td>Unknown</td><td>13</td><td>64</td><td>64/64</td><td>Unknown</td></tr><tr><td>C3</td><td>Ezra</td><td>800–1000</td><td>100–133</td><td>2002</td><td>130</td><td>Unknown</td><td>8.3–10</td><td>64</td><td>64/64</td><td>Unknown</td></tr><tr><td>C3</td><td>Nehemiah</td><td>1000–1400</td><td>133–200</td><td>2003</td><td>130</td><td>35×35</td><td>15–21</td><td>64</td><td>64/64</td><td>Unknown</td></tr><tr><td>C3-M</td><td>Nehemiah</td><td>1000–1400</td><td>133–200</td><td>2003</td><td>130</td><td>35×35</td><td>11–19</td><td>64</td><td>64/64</td><td>Unknown</td></tr><tr><th rowspan="3"><a href="/facts/VIA_C7/a4nqwGyr">C7</a></th><td>C7-D</td><td>Esther</td><td>1500–1800</td><td>400</td><td>2006</td><td>90</td><td>21×21</td><td>20–25</td><td>128</td><td>16/16</td><td>Unknown</td></tr><tr><td>C7-M</td><td>Esther</td><td>1000–2000</td><td>400</td><td>2005</td><td>90</td><td>21×21</td><td>12–20</td><td>128</td><td>16/16</td><td>Unknown</td></tr><tr><td>C7</td><td>Esther</td><td>1500–2000</td><td>800</td><td>2007</td><td>90</td><td>21×21</td><td>12–20</td><td>128</td><td>16/16</td><td>Unknown</td></tr></tbody></table> <h3><a href="/facts/VIA_Nano/82nYJeBy">Nano</a></h3> <ul><li>First VIA processor with <a href="/facts/X86-64/cyWvUFlP">x86-64</a> instruction set</li></ul> <table><tbody><tr><th>Series</th><th>Model</th><th>Core</th><th>Frequency[MHz]</th><th><a href="/facts/Front-side_bus/LgYSB7Wl">Front-side bus</a>[MHz]</th><th>Year</th><th>Process[nm]</th><th>Package size[mm2]</th><th>Power[W]</th><th>L2 cache[K]</th><th>L1 I/D cache[K]</th><th>Performance[SPEC2000]</th></tr><tr><th><a href="/facts/VIA_QuadCore/82nYJeBy">QuadCore</a></th><td>QuadCore</td><td>Isaiah</td><td>1000-1460</td><td>1066</td><td>2011</td><td>40</td><td>21×21</td><td>27.5</td><td>4× 1024<a class="footnote-ref" id="fnref:4" href="#fn:4"><sup>4</sup></a></td><td>4× 64/64</td><td>30.1/24.1 rate<a class="footnote-ref" id="fnref:5" href="#fn:5"><sup>5</sup></a></td></tr></tbody></table> <ul><li>See <a href="/facts/List_of_VIA_Nano_microprocessors/PUJggLYH">List of Nano microprocessors</a></li></ul> <h3>CHA</h3> <p class="note">Main article: <a href="/facts/Centaur_Technology/blY0qw55">Centaur Technology § CNS core</a></p> <ul><li>Announced 2019.<a class="footnote-ref" id="fnref:6" href="#fn:6"><sup>6</sup></a><a class="footnote-ref" id="fnref:7" href="#fn:7"><sup>7</sup></a><a class="footnote-ref" id="fnref:8" href="#fn:8"><sup>8</sup></a> Discontinued in 2021 with the sales of Centaur to Intel.<a class="footnote-ref" id="fnref:9" href="#fn:9"><sup>9</sup></a></li> <li>8 cores + "NCORE" neural processor for AI acceleration.</li> <li>supports: MMX SSE SSE2 SSE3 SSSE3 SSE4.1 SSE4.2 AES AVX AVX2 FMA3 SHA AVX512 AVX512F AVX512CD AVX512BW AVX512DQ AVX512VL AVX512IFMA AVX512VBMI.</li></ul> <table><tbody><tr><th>Marketingname</th><th>Code name</th><th>Core</th><th>Number of cores</th><th>Frequency</th><th>Microarchitecture</th><th>L1 cache</th><th>L2 cache</th><th>L3 cache</th><th>Announced</th><th>Expected Release</th><th>Process</th><th>Socket Type</th><th>Pipeline stages</th><th>PCIe Lanes</th></tr><tr><td>unknown</td><td>CHA</td><td>CNS</td><td>8</td><td>2.5 GHz</td><td>CNS<a class="footnote-ref" id="fnref:10" href="#fn:10"><sup>10</sup></a></td><td>32 KiB</td><td>256 KiB</td><td>16 MB</td><td>2019</td><td>2H 2020<a class="footnote-ref" id="fnref:11" href="#fn:11"><sup>11</sup></a></td><td>16 nm</td><td>LGA</td><td>20-22</td><td>44<a class="footnote-ref" id="fnref:12" href="#fn:12"><sup>12</sup></a></td></tr></tbody></table> <h2 id="see-also">See also</h2> <ul><li><a href="/facts/List_of_VIA_C3_microprocessors/6Q34keT6">List of VIA C3 microprocessors</a></li> <li><a href="/facts/List_of_VIA_C7_microprocessors/0Mah5dyr">List of VIA C7 microprocessors</a></li> <li><a href="/facts/List_of_VIA_Eden_microprocessors/LrYxo1R4">List of VIA Eden microprocessors</a></li> <li><a href="/facts/List_of_VIA_Nano_microprocessors/PUJggLYH">List of VIA Nano microprocessors</a></li></ul> <h2 id="external-links">External links</h2> <ul><li><a href="http://www.via.com.tw/en/products/processors/c3/">Via C3 product page</a> <a href="https://web.archive.org/web/20070502102646/http://www.via.com.tw/en/products/processors/c3/">Archived</a> 2007-05-02 at the <a href="/facts/Wayback_Machine/nmQ3a6JC">Wayback Machine</a></li> <li><a href="http://www.via.com.tw/en/products/processors/c7/">Via C7 product page</a> <a href="https://web.archive.org/web/20070419142654/http://www.via.com.tw/en/products/processors/c7-m/">Archived</a> 2007-04-19 at the <a href="/facts/Wayback_Machine/nmQ3a6JC">Wayback Machine</a></li> <li><a href="http://www.via.com.tw/en/products/processors/nano/">Via Nano product page</a> <a href="https://web.archive.org/web/20080530071601/http://www.via.com.tw/en/products/processors/nano/">Archived</a> 2008-05-30 at the <a href="/facts/Wayback_Machine/nmQ3a6JC">Wayback Machine</a></li></ul> <h2 id="references">References</h2> <ol> <li id="fn:1"><p>"IA-32 implementation: VIA Cyrix III". sandpile.org. Archived from the original on 2007-07-09. Retrieved 2007-07-23. <a href="https://web.archive.org/web/20070709200826/http://www.sandpile.org/impl/m2c3.htm" target="_blank">https://web.archive.org/web/20070709200826/http://www.sandpile.org/impl/m2c3.htm</a> <a href="#fnref:1" class="footnote-back-ref">↩</a></p></li> <li id="fn:2"><p>"IA-32 implementation: VIA C3". sandpile.org. Archived from the original on 2007-07-17. Retrieved 2007-07-23. <a href="https://web.archive.org/web/20070717014946/http://www.sandpile.org/impl/c5.htm" target="_blank">https://web.archive.org/web/20070717014946/http://www.sandpile.org/impl/c5.htm</a> <a href="#fnref:2" class="footnote-back-ref">↩</a></p></li> <li id="fn:3"><p>"IA-32 implementation: VIA C7". sandpile.org. Archived from the original on 2007-06-30. Retrieved 2007-07-23. <a href="https://web.archive.org/web/20070630151130/http://www.sandpile.org/impl/c5xl.htm" target="_blank">https://web.archive.org/web/20070630151130/http://www.sandpile.org/impl/c5xl.htm</a> <a href="#fnref:3" class="footnote-back-ref">↩</a></p></li> <li id="fn:4"><p>"VIA QuadCore Processor". Via.com. Retrieved 2014-02-03. <a href="http://www.via.com.tw/en/products/processors/quadcore/index.jsp" target="_blank">http://www.via.com.tw/en/products/processors/quadcore/index.jsp</a> <a href="#fnref:4" class="footnote-back-ref">↩</a></p></li> <li id="fn:5"><p>"VIA Nano X2 Whitepaper" (PDF). Via.com. Archived from the original (PDF) on 27 May 2012. Retrieved 3 February 2014. <a href="https://web.archive.org/web/20120527051549/http://www.via.com.tw/en/downloads/whitepapers/processors/NanoX2_whitepaper_201107.pdf" target="_blank">https://web.archive.org/web/20120527051549/http://www.via.com.tw/en/downloads/whitepapers/processors/NanoX2_whitepaper_201107.pdf</a> <a href="#fnref:5" class="footnote-back-ref">↩</a></p></li> <li id="fn:6"><p>"VIA CenTaur Develops a Multi-core x86 Processor for Enterprise with in-built AI Hardware". TechPowerUp. November 18, 2019h. Retrieved 2020-07-28. <a href="https://www.techpowerup.com/261274/via-centaur-develops-a-multi-core-x86-processor-for-enterprise-with-in-built-ai-hardware" target="_blank">https://www.techpowerup.com/261274/via-centaur-develops-a-multi-core-x86-processor-for-enterprise-with-in-built-ai-hardware</a> <a href="#fnref:6" class="footnote-back-ref">↩</a></p></li> <li id="fn:7"><p>"VIA CenTaur CHA NCORE AI CPU Pictured, a Socketed LGA Package". TechPowerUp. February 18, 2020. Retrieved 2020-07-28. <a href="https://www.techpowerup.com/263978/via-centaur-cha-ncore-ai-cpu-pictured-a-socketed-lga-package" target="_blank">https://www.techpowerup.com/263978/via-centaur-cha-ncore-ai-cpu-pictured-a-socketed-lga-package</a> <a href="#fnref:7" class="footnote-back-ref">↩</a></p></li> <li id="fn:8"><p>"CHA - Microarchitectures - Centaur Technology - WikiChip". en.wikichip.org. Retrieved 2020-07-28. <a href="https://en.wikichip.org/wiki/centaur/microarchitectures/cha" target="_blank">https://en.wikichip.org/wiki/centaur/microarchitectures/cha</a> <a href="#fnref:8" class="footnote-back-ref">↩</a></p></li> <li id="fn:9"><p>"The Last x86 Via Chip: Unreleased Next-Gen Centaur CNS Saved From Trash Bin, Tested". TomsHardware. 22 February 2022. <a href="https://www.tomshardware.com/news/last-x86-via-chip-centuar-cns-cpu-tested" target="_blank">https://www.tomshardware.com/news/last-x86-via-chip-centuar-cns-cpu-tested</a> <a href="#fnref:9" class="footnote-back-ref">↩</a></p></li> <li id="fn:10"><p>"VIA x86 AI processor architecture, performance announcement: comparable to Intel 32 core". Small Tech News. December 11, 2019. <a href="https://www.smalltechnews.com/archives/36581" target="_blank">https://www.smalltechnews.com/archives/36581</a> <a href="#fnref:10" class="footnote-back-ref">↩</a></p></li> <li id="fn:11"><p>"Centaur Releases In-Depth Analysis from The Linley Group for its NCORE-Equipped x86 Processor". TechPowerUp. December 9, 2019. Retrieved 2020-08-30. <a href="https://www.techpowerup.com/261979/centaur-releases-in-depth-analysis-from-the-linley-group-for-its-ncore-equipped-x86-processor" target="_blank">https://www.techpowerup.com/261979/centaur-releases-in-depth-analysis-from-the-linley-group-for-its-ncore-equipped-x86-processor</a> <a href="#fnref:11" class="footnote-back-ref">↩</a></p></li> <li id="fn:12"><p>"World's First High-Performancex86 SoCwithIntegrated AI Coprocessor" (PDF). centtech. p. 4. Archived from the original on November 19, 2019. <a href="https://web.archive.org/web/20191119163412/https://centtech.com/wp-content/uploads/PRSlides_1118_Release.pdf" target="_blank">https://web.archive.org/web/20191119163412/https://centtech.com/wp-content/uploads/PRSlides_1118_Release.pdf</a> <a href="#fnref:12" class="footnote-back-ref">↩</a></p></li> </ol>