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VerilogCSP
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<p>In <a href="/facts/Integrated_circuit_design/sE0qVzyo">integrated circuit design</a>, VerilogCSP is a set of <a href="/facts/Macro_(computer_science)/7abAsm1o">macros</a> added to <a href="/facts/Verilog_HDL/efVqbKXg">Verilog HDL</a> to support <a href="/facts/Communicating_Sequential_Processes/bzKGnJ50">Communicating Sequential Processes</a> (CSP) channel communications. These macros are intended to be used in designing <a href="/facts/Asynchronous_circuit/n4ah2j7H">digital asynchronous circuits</a>. VerilogCSP also describes nonlinear <a href="/facts/Pipeline_(computing)/xmHjrPMP">pipelines</a> and high-level channel timing properties, such as forward and backward <a href="/facts/Latency_(engineering)/6Bjhn30H">latencies</a>, minimum cycle time, and slack. </p>