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Hybrid-core computing
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<p>Hybrid-core computing is the technique of extending a commodity <a href="/facts/Instruction_set_architecture/8p8vwUeE">instruction set architecture</a> (e.g. <a href="/facts/X86/Kypq5fgu">x86</a>) with application-specific instructions to accelerate application performance. It is a form of <a href="/facts/Heterogeneous_computing/FYkECQ75">heterogeneous computing</a> wherein asymmetric computational units coexist with a "commodity" processor. </p><p>Hybrid-core processing differs from general heterogeneous computing in that the computational units share a common logical address space, and an executable is composed of a single instruction stream—in essence a contemporary <a href="/facts/Coprocessor/WsVXzAGo">coprocessor</a>. The instruction set of a hybrid-core computing system contains instructions that can be dispatched either to the host instruction set or to the application-specific hardware. </p><p>Typically, hybrid-core computing is best deployed where the predominance of computational cycles are spent in a few identifiable kernels, as is often seen in <a href="/facts/High-performance_computing/HT9NwGAN">high-performance computing</a> applications. Acceleration is especially pronounced when the kernel's logic maps poorly to a sequence of commodity processor instructions, and/or maps well to the application-specific hardware. </p><p>Hybrid-core computing is used to accelerate applications beyond what is currently physically possible with off-the-shelf processors, or to lower power & cooling costs in a data center by reducing computational footprint. (i.e., to circumvent obstacles such as the power/density challenges faced with today's commodity processors). </p>