Latency oriented processor architecture

<p>Latency oriented processor architecture is the <a href="/facts/Microarchitecture/NFRd4NUL">microarchitecture</a> of a <a href="/facts/Microprocessor/Fx9CaQht">microprocessor</a> designed to serve a serial computing <a href="/facts/Thread_(computing)/hh8WHyPd">thread</a> with a low latency. This is typical of most <a href="/facts/Central_processing_unit/Jxp1bqMV">central processing units</a> (CPU) being developed since the 1970s. These architectures, in general, aim to execute as many instructions as possible belonging to a single serial thread, in a given window of time; however, the time to execute a single instruction completely from fetch to retire stages may vary from a few cycles to even a few hundred cycles in some cases. Latency oriented processor architectures are the opposite of throughput-oriented processors which concern themselves more with the total <a href="/facts/Throughput/6zAUsXqw">throughput</a> of the system, rather than the service <a href="/facts/Latency_(engineering)/6Bjhn30H">latencies</a> for all individual threads that they work on.
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Latency oriented processor architecture open-in-new

Latency oriented processor architecture