Classic RISC pipeline

<p>In the <a href="/facts/History_of_computing_hardware/83xXSmuW">history of computer hardware</a>, some early <a href="/facts/Reduced_instruction_set_computer/aQbGM62p">reduced instruction set computer</a> <a href="/facts/Central_processing_unit/Jxp1bqMV">central processing units</a> (RISC CPUs) used a very similar architectural solution, now called a classic RISC pipeline. Those CPUs were: <a href="/facts/MIPS_architecture/efV4KgK4">MIPS</a>, <a href="/facts/SPARC/m7KhEtET">SPARC</a>, Motorola <a href="/facts/Motorola_88000/7GfVFIWo">88000</a>, and later the notional CPU <a href="/facts/DLX/ehqMj5Kh">DLX</a> invented for education.
</p><p>Each of these classic scalar RISC designs fetches and tries to execute one <a href="/facts/Instructions_per_cycle/nHl8f6Ho">instruction per cycle</a>.  The main common concept of each design is a five-stage execution <a href="/facts/Instruction_pipeline/3zy6CcX1">instruction pipeline</a>.  During operation, each pipeline stage works on one instruction at a time.  Each of these stages consists of a set of <a href="/facts/Flip-flop_(electronics)/vA99xjM7">flip-flops</a> to hold state, and <a href="/facts/Combinational_logic/L1kaaVK5">combinational logic</a> that operates on the outputs of those flip-flops.
</p>

Classic RISC pipeline open-in-new

Classic RISC pipeline