MESI protocol

<p>The MESI protocol is an invalidate-based <a href="/facts/List_of_cache_coherency_protocols/jJMeunvS">cache coherence protocol</a>, and is one of the most common protocols that support <a href="/facts/Write-back_cache/gmJYN8wm">write-back caches</a>. It is also known as the Illinois protocol due to its development at the <a href="/facts/University_of_Illinois_Urbana-Champaign/gusw7HoS">University of Illinois at Urbana-Champaign</a>. Write back caches can save considerable bandwidth generally wasted on a <a href="/facts/Cache_(computing)/gmJYN8wm">write through cache</a>. There is always a dirty state present in write-back caches that indicates that the data in the cache is different from that in the main memory. The Illinois Protocol requires a cache-to-cache transfer on a miss if the block resides in another cache. This protocol reduces the number of main memory transactions with respect to the <a href="/facts/MSI_protocol/YjNNNoGU">MSI protocol</a>. This marks a significant improvement in performance.
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MESI protocol open-in-new

MESI protocol