Chip-scale package

A chip scale package or chip-scale package (CSP) is a type of <a href="/facts/Integrated_circuit/fjn6vg7C">integrated circuit</a> package.
Originally, CSP was the acronym for chip-size packaging. Since only a few packages are chip size, the meaning of the acronym was adapted to chip-scale packaging. According to <a href="/facts/IPC_(electronics)/Db8nM9TY">IPC</a>'s standard J-STD-012, Implementation of Flip Chip and Chip Scale Technology, in order to qualify as chip scale, the package must have an area no greater than 1.2 times that of the <a href="/facts/Die_(integrated_circuit)/XWvdlltE">die</a> and it must be a single-die, direct surface mountable package. Another criterion that is often applied to qualify these packages as CSPs is their ball pitch should be no more than 1 mm.
The concept was first proposed by Junichi Kasai of <a href="/facts/Fujitsu/6e5gvNSa">Fujitsu</a> and Gen Murakami of <a href="/facts/Hitachi_Cable/v06Bnh5h">Hitachi Cable</a> in 1993. The first concept demonstration however came from <a href="/facts/Mitsubishi_Electric/aRfAQNS8">Mitsubishi Electric</a>.
The die may be mounted on an <a href="/facts/Interposer/nkQ2YKQQ">interposer</a> upon which pads or balls are formed, like with <a href="/facts/Flip_chip/2jleJDJI">flip chip</a> <a href="/facts/Ball_grid_array/0sjfGthJ">ball grid array</a> (BGA) packaging, or the pads may be etched or printed directly onto the <a href="/facts/Silicon_wafer/lCBJAoUL">silicon wafer</a>, resulting in a package very close to the size of the silicon die: such a package is called a <a href="/facts/Wafer-level_package/2uFHt6cc">wafer-level package</a> (WLP) or a wafer-level chip-scale package (WL-CSP). WL-CSP had been in development since 1990s, and several companies begun volume production in early 2000, such as <a href="/facts/Advanced_Semiconductor_Engineering/eqX5YkeJ">Advanced Semiconductor Engineering</a> (ASE).

Chip-scale package open-in-new

Chip-scale package