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CoreConnect
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<p>CoreConnect is a <a href="/facts/Microprocessor/Fx9CaQht">microprocessor</a> <a href="/facts/Bus_(computing)/R45TKwS7">bus</a>-architecture from <a href="/facts/IBM/QszA7nwd">IBM</a> for <a href="/facts/System-on-a-chip/1RVvVe6N">system-on-a-chip</a> (SoC) designs. It was designed to ease the integration and reuse of processor, system, and peripheral <a href="/facts/Multi-core_(computing)/ABNb65hQ">cores</a> within standard and custom SoC designs. As a standard SoC design point, it serves as the foundation of IBM or non-IBM devices. Elements of this architecture include the processor local bus (PLB), the on-chip peripheral bus (OPB), a bus bridge, and a <a href="/facts/Device_control_register/LK34HK7M">device control register</a> (DCR) bus. High-performance peripherals connect to the high-<a href="/facts/Bit_rate/ppUNMmVd">bandwidth</a>, low-<a href="/facts/Latency_(engineering)/6Bjhn30H">latency</a> PLB. Slower peripheral cores connect to the OPB, which reduces traffic on the PLB. CoreConnect has bridging capabilities to the competing <a href="/facts/Advanced_Microcontroller_Bus_Architecture/LXPA3SnW">AMBA</a> bus architecture, allowing reuse of existing SoC-components. </p><p>IBM makes the CoreConnect bus available as a no-fee, no-royalty architecture to tool-vendors, core IP-companies, and chip-development companies. As such it is licensed by over 1500 electronics companies such as <a href="/facts/Cadence_Design_Systems/6pTzpgFc">Cadence</a>, <a href="/facts/Ericsson/yJ4oMMp7">Ericsson</a>, <a href="/facts/Lucent/uzgpVmLa">Lucent</a>, <a href="/facts/Nokia/bCleFoF4">Nokia</a>, <a href="/facts/Siemens/coa80TQn">Siemens</a> and <a href="/facts/Synopsys/Szv1V36J">Synopsys</a>. </p><p>The CoreConnect is an integral part of IBM's embedded offerings and is used extensively in their <a href="/facts/PowerPC_400/X6zS1Rgu">PowerPC 4x0</a> based designs. In the past, <a href="/facts/Xilinx/rbXfxqqG">Xilinx</a> was using CoreConnect as the infrastructure for all of their embedded processor designs. </p>