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IEEE 1164
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Character literals<a class="footnote-ref" id="fnref:1" href="#fn:1"><sup>1</sup></a><table><tbody><tr><th>Character</th><th>Value</th></tr><tr><td>'U'</td><td>uninitialized</td></tr><tr><td>'X'</td><td>strong drive, unknown logic value</td></tr><tr><td>'0'</td><td>strong drive, logic zero</td></tr><tr><td>'1'</td><td>strong drive, logic one</td></tr><tr><td>'Z'</td><td>high impedance</td></tr><tr><td>'W'</td><td>weak drive, unknown logic value</td></tr><tr><td>'L'</td><td>weak drive, logic zero</td></tr><tr><td>'H'</td><td>weak drive, logic one</td></tr><tr><td>'-'</td><td><a href="/facts/Don%27t-care_term/kvQuwYMK">don't care</a></td></tr></tbody></table> <p>The IEEE 1164 standard (<i>Multivalue Logic System for VHDL Model Interoperability</i>) is a technical standard published by the IEEE in 1993. It describes the definitions of logic values to be used in <a href="/facts/Electronic_design_automation/o4la3fmX">electronic design automation</a>, for the <a href="/facts/VHDL/H6Exdjfs">VHDL</a> hardware description language. It was sponsored by the <a href="/facts/Design_Automation_Standards_Committee/c0nIYrUu">Design Automation Standards Committee</a> of the <a href="/facts/Institute_of_Electrical_and_Electronics_Engineers/UddC4pUW">Institute of Electrical and Electronics Engineers</a> (IEEE). The standardization effort was based on the donation of the <a href="/facts/Synopsys/Szv1V36J">Synopsys</a> MVL-9 type declaration. </p><p>The primary data type std_ulogic (standard unresolved logic) consists of nine character literals (see table on the right). This system promoted a useful set of logic values that typical CMOS logic designs could implement in the vast majority of modeling situations, including: </p> <ul><li>'Z' literal to make <a href="/facts/Three-state_logic/SD6wXHNN">tri-state buffer</a> logic easy</li> <li>'H' and 'L' weak drives to permit <a href="/facts/Wired_logic_connection/1YduGEtl">wired-AND</a> and <a href="/facts/Wired_logic_connection/1YduGEtl">wired-OR</a> logic.</li> <li>'U' for default value for all object declarations so that during simulations uninitialized values are easily detectable and thus easily corrected if necessary.</li></ul> <p>In <a href="/facts/VHDL/H6Exdjfs">VHDL</a>, the hardware designer makes the declarations visible via the following library and use statements: </p> library IEEE; use IEEE.std_logic_1164.all;