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Intel 5-level paging
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<p>Intel 5-level paging, referred to simply as <i>5-level paging</i> in <a href="/facts/Intel/SMF0gJJX">Intel</a> documents, is a processor extension for the <a href="/facts/X86-64/cyWvUFlP">x86-64</a> line of processors.: 11 It extends the size of <a href="/facts/Virtual_address/ILxbMjgv">virtual addresses</a> from 48 bits to 57 bits by adding an additional level to x86-64's <a href="/facts/Page_table/0IBU5cwg">multilevel page tables</a>, increasing the addressable <a href="/facts/Virtual_memory/Lw2GemF5">virtual memory</a> from 256 <a href="/facts/Tebibyte/BNHUp9Qq">TiB</a> to 128 <a href="/facts/Pebibyte/BNHUp9Qq">PiB</a>. The extension was first implemented in the <a href="/facts/Ice_Lake_(microprocessor)/ezzrBUW5">Ice Lake</a> processors. </p>