Logic redundancy

Logic redundancy occurs in a <a href="/facts/Logic_gate/RHLulvKI">digital gate</a> network containing circuitry that does not affect the static logic function. There are several reasons why logic redundancy may exist. One reason is that it may have been added deliberately to suppress transient glitches (thus causing a <a href="/facts/Race_condition/bvNpgy4F">race condition</a>) in the output signals by having two or more product terms overlap with a third one.
Consider the following equation:

Y
        =
        A
        B
        +
        
          
            A
            ¯
          
        
        C
        +
        B
        C
        .
      
    
    {\displaystyle Y=AB+{\overline {A}}C+BC.}

The third product term 
 
 
 
 B
 C
 
 
 {\displaystyle BC}
 
 is a redundant <a href="/facts/Consensus_theorem/D3g60g8a">consensus term</a>. If 
 
 
 
 A
 
 
 {\displaystyle A}
 
 switches from 1 to 0 while 
 
 
 
 B
 =
 1
 
 
 {\displaystyle B=1}
 
 and 
 
 
 
 C
 =
 1
 
 
 {\displaystyle C=1}
 
, 
 
 
 
 Y
 
 
 {\displaystyle Y}
 
 remains 1. During the transition of signal 
 
 
 
 A
 
 
 {\displaystyle A}
 
 in logic gates, both the first and second term may be 0 momentarily. The third term prevents a glitch since its value of 1 in this case is not affected by the transition of signal 
 
 
 
 A
 
 
 {\displaystyle A}
 
.
Another reason for logic redundancy is poor design practices which unintentionally result in logically redundant terms. This causes an unnecessary increase in network complexity, and possibly hampering the ability to test manufactured designs using traditional test methods (single stuck-at fault models). Testing might be possible using <a href="/facts/Iddq_testing/x5WFd5CJ">IDDQ</a> models.

Logic redundancy open-in-new

Logic redundancy