Capability Hardware Enhanced RISC Instructions

Capability Hardware Enhanced RISC Instructions (CHERI) is a technology designed to improve security for <a href="/facts/Reduced_instruction_set_computer/aQbGM62p">reduced instruction set computer</a> (RISC) processors. CHERI aims to address the root cause of the problems caused by lack of <a href="/facts/Memory_safety/sMWW6SY8">memory safety</a> in common implementations of <a href="/facts/Programming_language/cWTYbgWa">programming languages</a> such as <a href="/facts/C_(programming_language)/Ky2No763">C</a> and <a href="/facts/C%252B%252B/Et0F2qn9">C++</a>, which are responsible for around 70% of security vulnerabilities in modern systems.
The hardware works by giving each reference to any piece of data or system resource its own access rules. This prevents programs from accessing or changing things they should not. It also makes it hard to trick a part of a program into accessing or changing something that it should be able to access, but at a different time. The same mechanism is used to implement <a href="/facts/Privilege_separation/gLMQVMrp">privilege separation</a>, dividing processes into compartments that limit the damage that a bug (security or otherwise) can do.
CHERI can be added to many different <a href="/facts/Instruction_set_architecture/8p8vwUeE">instruction set architectures</a> including <a href="/facts/MIPS_architecture/efV4KgK4">MIPS</a>, <a href="/facts/AArch64/bauXRos7">AArch64</a>, and <a href="/facts/RISC-V/pUSKDat1">RISC-V</a>, making it usable across a wide range of platforms.
Software must be recompiled to gain fine-grained memory-safety benefits from CHERI, but most software requires few (if any) changes to the source code. CHERI's importance has been recognised by governments as a way to improve cybersecurity and protect critical systems. It is under active development by various business and academic organizations.

Capability Hardware Enhanced RISC Instructions open-in-new

Capability Hardware Enhanced RISC Instructions