Open Verification Methodology

<p>The Open Verification Methodology (OVM) is a documented <a href="/facts/Methodology/dk5X9Hxx">methodology</a> with a supporting building-block library for the verification of semiconductor chip designs. The initial version, OVM 1.0, was released in January, 2008, and regular updates have expanded its functionality. The latest version is OVM 2.1.2, released in January, 2011.
</p><p>The reuse concepts within the OVM were derived mainly from the Universal Reuse Methodology (URM) which was, to a large part, based on the <a href="/facts/E_Reuse_Methodology/2VWGacn3">e Reuse Methodology</a> (ERM) for the <a href="/facts/E_(verification_language)/hRaWFL4S">e Verification Language</a> developed by Verisity Design in 2001.  The OVM also brings in concepts from the Advanced Verification Methodology (AVM).  The <a href="/facts/Universal_Verification_Methodology/0L48MyMh">UVM</a> class library brings much automation to the <a href="/facts/SystemVerilog/wkBdc179">SystemVerilog</a> language such as sequences and data automation features (packing, copy, compare, etc.).  The UVM also has recommendations for code packaging and naming conventions.
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Open Verification Methodology open-in-new

Open Verification Methodology