SPARC T5

SPARC T5 is the fifth generation <a href="/facts/Multi-core_processor/ABNb65hQ">multicore microprocessor</a> of <a href="/facts/Oracle_Corporation/0z14FygH">Oracle's</a> <a href="/facts/SPARC_T_series/Vco4hf0m">SPARC T series</a> family. It was first presented at Hot Chips 24 in August 2012, and was officially introduced with the Oracle <a href="/facts/SPARC_T_series/Vco4hf0m">SPARC T5 servers</a> in March 2013. The processor is designed to offer high multithreaded performance (16 cores per chip, with 8 threads per core), as well as high single threaded performance from the same chip.
The processor uses the same SPARC S3 core design as its predecessor, the <a href="/facts/SPARC_T4/kTyoPJnW">SPARC T4</a> processor, but is implemented in a 28 nm process and runs at 3.6 GHz. The S3 core is a dual-issue core that uses dynamic <a href="/facts/Multithreading_(computer_architecture)/ojEKsSNP">threading</a> and <a href="/facts/Out-of-order_execution/bM0dQM8m">out-of-order execution</a>, incorporates one <a href="/facts/Floating-point_unit/XWTW2AbF">floating point unit</a>, one dedicated <a href="/facts/Cryptography/e94PEVau">cryptographic</a> unit per core.
The 64-bit SPARC Version 9 based processor has 16 cores supporting up to 128 threads per processor, and scales up to 1,024 threads in an 8 <a href="/facts/CPU_socket/ndWcsnq6">socket</a> system. Other changes include the support of PCIe version 3.0 and a new cache coherence protocol.

SPARC T5 open-in-new

SPARC T5