S1 Core

<p>S1 Core (codename Sirocco) is an <a href="/facts/Open_source_hardware/UgCHeVsm">open source hardware</a> <a href="/facts/Microprocessor/Fx9CaQht">microprocessor</a> design developed by Simply RISC. Based on <a href="/facts/Sun_Microsystems/VJ9EzEFd">Sun Microsystems</a>' <a href="/facts/UltraSPARC_T1/mfxg7MjI">UltraSPARC T1</a>, the S1 Core is licensed under the <a href="/facts/GNU_General_Public_License/S75KhLSX">GNU General Public License</a>, which is the license Sun chose for the <a href="/facts/OpenSPARC/6cokbgCP">OpenSPARC</a> project.
</p><p>The main goal of the project is to keep the S1 Core as simple as possible to encourage developers. The major differences between T1 and S1 include:
</p>
<ul><li>S1 Core only has one 64-bit <a href="/facts/SPARC/m7KhEtET">SPARC</a> Core (supporting one to four independent threads of execution) instead of eight cores;</li>
<li>S1 Core adds a <a href="/facts/Wishbone_(computer_bus)/xTu4vkDw">Wishbone</a> bridge, a reset controller and a basic <a href="/facts/Interrupt_controller/0ukSAuF1">interrupt controller</a>;</li>
<li>the S1 Core environment can be run using only free tools on a common x86 Linux machine.</li></ul>

S1 Core open-in-new

S1 Core