Wright etch

<p>The Wright etch (also Wright-Jenkins etch) is a preferential etch for revealing defects in <100>- and <111>-oriented, p- and n-type <a href="/facts/Silicon/cgWx0hdr">silicon</a> wafers used for making transistors, microprocessors, memories, and other components. Revealing, identifying, and remedying such defects is essential for progress along the path predicted by <a href="/facts/Moore%27s_law/90CSekhl">Moore's law</a>. It was developed by Margaret Wright Jenkins (1936-2018) in 1976 while working in <a href="/facts/Research_and_development/2h5UddUu">research and development</a> at <a href="/facts/Motorola_Inc./ztqczx68">Motorola Inc.</a> in Phoenix, AZ.  It was published in 1977. This etchant reveals clearly defined <a href="/facts/Oxidation/Pyd5RVcj">oxidation</a>-induced stacking faults, dislocations, swirls and striations with minimum surface roughness or extraneous pitting. These defects are known causes of shorts and current leakage in finished <a href="/facts/Semiconductor/zFf3mGTE">semiconductor</a> devices (such as <a href="/facts/Transistor/Bmr8zwL0">transistors</a>) should they fall across isolated junctions. A relatively low etch rate (~1 micrometre per minute) at room temperature provides etch control. The long shelf life of this etchant allows the solution to be stored in large quantities.
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Wright etch open-in-new

Wright etch