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Complex instruction set computer
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<p>A complex instruction set computer (CISC /ˈsɪsk/) is a <a href="/facts/Computer_architecture/tHtwxgR2">computer architecture</a> in which single <a href="/facts/Instruction_set_architecture/8p8vwUeE">instructions</a> can execute several low-level operations (such as a load from <a href="/facts/Memory_(computers)/hQKVQ51J">memory</a>, an <a href="/facts/Arithmetic/hvHwkbMV">arithmetic</a> <a href="/facts/Operator_(programming)/7TnU5LKu">operation</a>, and a memory store) or are capable of multi-step operations or <a href="/facts/Addressing_mode/g78wINgK">addressing modes</a> within single instructions. The term was retroactively coined in contrast to <a href="/facts/Reduced_instruction_set_computer/aQbGM62p">reduced instruction set computer</a> (RISC) and has therefore become something of an <a href="/facts/Umbrella_term/bjxUuoRb">umbrella term</a> for everything that is not RISC, where the typical differentiating characteristic[<i>dubious – discuss</i>] is that most RISC designs use uniform instruction length for almost all instructions, and employ strictly separate load and store instructions. </p><p>Examples of CISC architectures include complex <a href="/facts/Mainframe_computer/nrBR6rWa">mainframe computers</a> to simplistic microcontrollers where memory load and store operations are not separated from arithmetic instructions. Specific instruction set architectures that have been retroactively labeled CISC are <a href="/facts/System%2f360/7znvpy4K">System/360</a> through <a href="/facts/Z%2fArchitecture/FcKYkGn9">z/Architecture</a>, the <a href="/facts/PDP-11/9HkGUzFn">PDP-11</a> and <a href="/facts/VAX/N3r13IHH">VAX</a> architectures, and many others. Well known microprocessors and microcontrollers that have also been labeled CISC in many academic publications include the <a href="/facts/Motorola_6800/0D4BNIha">Motorola 6800</a>, <a href="/facts/6809/AM6UosAk">6809</a> and <a href="/facts/Motorola_68000_series/jxd7VPlW">68000</a> families; the Intel <a href="/facts/8080/32FvNTcD">8080</a>, <a href="/facts/IAPX_432/z0xPqFQf">iAPX 432</a>, <a href="/facts/X86/Kypq5fgu">x86</a> and <a href="/facts/8051/2bqJXGlv">8051</a> families; the Zilog <a href="/facts/Z80/Jeqe2h55">Z80</a>, <a href="/facts/Zilog_Z8/9RjqPUVV">Z8</a> and <a href="/facts/Z8000/do1uTklA">Z8000</a> families; the <a href="/facts/National_Semiconductor/xeAD8doA">National Semiconductor</a> <a href="/facts/NS32000/zCXoyxzh">NS320xx</a> family; the MOS Technology <a href="/facts/6502/q9YLwkzm">6502</a> family; and others. </p><p>Some designs have been regarded as borderline cases by some writers.[<i>who?</i>] For instance, the <a href="/facts/Microchip_Technology/7jDrY5rx">Microchip Technology</a> <a href="/facts/PIC_microcontroller/NrRJCqHS">PIC</a> has been labeled RISC in some circles and CISC in others. </p>