Altera Hardware Description Language

<p>Altera Hardware Description Language (AHDL) is a proprietary <a href="/facts/Hardware_description_language/g19KvKCu">hardware description language</a> (HDL) developed by <a href="/facts/Altera_Corporation/66c0Gh0R">Altera Corporation</a>. AHDL is used for <a href="/facts/Digital_logic/RHLulvKI">digital logic</a> design entry for Altera's <a href="/facts/Complex_programmable_logic_device/CUKHIAID">complex programmable logic devices</a> (CPLDs) and <a href="/facts/Field-programmable_gate_array/M8LSGcAU">field-programmable gate arrays</a> (FPGAs). It is supported by Altera's MAX-PLUS and <a href="/facts/Altera_Quartus/28K9Nq7M">Quartus</a> series of design software. AHDL has an <a href="/facts/Ada_programming_language/Y2yHel4l">Ada</a>-like syntax, while its feature set is comparable to the synthesizable portions of the <a href="/facts/Verilog/efVqbKXg">Verilog</a> and <a href="/facts/VHDL/H6Exdjfs">VHDL</a> hardware description languages. In contrast to HDLs such as Verilog and VHDL, AHDL is a design-entry language only; all of its language constructs are synthesizable. By default, Altera software expects AHDL source files to have a .tdf extension (Text Design Files).
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Altera Hardware Description Language open-in-new

Altera Hardware Description Language