Zilog Z8000

The Zilog Z8000 is a <a href="/facts/16-bit_computing/bTGS44Ne">16-bit</a> microprocessor architecture designed by <a href="/facts/Zilog/sB6jH5vw">Zilog</a> and introduced in early 1979. Two chips were initially released, differing only in the width of the address bus; the Z8001 had a 23-bit bus while the Z8002 had a 16-bit bus.
Bernard Peuto designed the architecture, while <a href="/facts/Masatoshi_Shima/H83xJqVQ">Masatoshi Shima</a> did the logic and physical implementation, assisted by a small group. In contrast to most designs of the era, the Z8000 does not use <a href="/facts/Microcode/XQEsr2X3">microcode</a>, which allowed it to be implemented in only 17,500 transistors. The Z8000 is not <a href="/facts/Zilog_Z80/Jeqe2h55">Z80</a>-compatible, but includes a number of design elements from it, such as combining two registers into one with twice the number of bits. The Z8000 expanded on the Z80 by allowing two 16-bit registers to operate as a 32-bit register, or four to operate as a 64-bit register.
Although it saw some use in the early 1980s, it was never as popular as the Z80. It was released after the 16-bit <a href="/facts/Intel_8086/sS9dlSdK">8086</a> (April 1978) and the same time as the less-expensive <a href="/facts/Intel_8088/DdWKfyBp">8088</a>, and only months before the <a href="/facts/Motorola_68000/3p2wt2D6">68000</a> (September 1979) with a 32-bit <a href="/facts/Instruction_set_architecture/8p8vwUeE">instruction set architecture</a> and which is roughly twice as fast. The <a href="/facts/Zilog_Z80000/6QjjyMr1">Z80000</a> was a 32-bit follow-on design that made it to a test sampling phase in 1986 without ever being released commercially.

Zilog Z8000 open-in-new

Zilog Z8000