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Reference.org
Pipeline stall
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<p>In the design of <a href="/facts/Instruction_pipeline/3zy6CcX1">pipelined computer processors</a>, a pipeline stall is a delay in execution of an <a href="/facts/Instruction_set/8p8vwUeE">instruction</a> in order to resolve a <a href="/facts/Hazard_(computer_architecture)/hXItYfk1">hazard</a>. </p>