Single instruction, multiple data

Single instruction, multiple data (SIMD) is a type of <a href="/facts/Parallel_computer/nQzcpzQt">parallel processing</a> in <a href="/facts/Flynn%2527s_taxonomy/VrmXKDTA">Flynn's taxonomy</a>. SIMD describes computers with <a href="/facts/Multiple_processing_elements/nQzcpzQt">multiple processing elements</a> that perform the same operation on multiple data points simultaneously. SIMD can be internal (part of the hardware design) and it can be directly accessible through an <a href="/facts/Instruction_set_architecture/8p8vwUeE">instruction set architecture</a> (ISA), but it should not be confused with an ISA. 
Such machines exploit <a href="/facts/Data_parallelism/SkYoL91S">data level parallelism</a>, but not <a href="/facts/Concurrent_computing/yVzQBPr9">concurrency</a>: there are simultaneous (parallel) computations, but each unit performs exactly the same instruction at any given moment (just with different data). A simple example is to add many pairs of numbers together, all of the SIMD units are performing an addition, but each one has different pairs of values to add. SIMD is particularly applicable to common tasks such as adjusting the contrast in a <a href="/facts/Digital_image/3TNT47Mv">digital image</a> or adjusting the volume of <a href="/facts/Digital_audio/PgugcLAI">digital audio</a>. Most modern <a href="/facts/Central_processing_unit/Jxp1bqMV">CPU</a> designs include SIMD instructions to improve the performance of <a href="/facts/Multimedia/PtJteq27">multimedia</a> use. In recent CPUs, SIMD units are tightly coupled with cache hierarchies and prefetch mechanisms, which minimize latency during large block operations. For instance, AVX-512-enabled processors can prefetch entire cache lines and apply fused multiply-add operations (FMA) in a single SIMD cycle.
SIMD has three different subcategories in <a href="/facts/Flynn%2527s_taxonomy/VrmXKDTA">Flynn's 1972 Taxonomy</a>, one of which is <a href="/facts/Single_instruction%2c_multiple_threads/kRaRt8NX">SIMT</a>. SIMT should not be confused with <a href="/facts/Thread_(computing)/hh8WHyPd">software threads</a> or <a href="/facts/Multithreading_(computer_architecture)/ojEKsSNP">hardware threads</a>, both of which are task time-sharing (time-slicing). SIMT is true simultaneous parallel hardware-level execution. A key distinction in SIMT is the presence of control flow mechanisms like warps (NVIDIA terminology) or wavefronts (AMD terminology). These allow divergence and convergence of threads, even under shared instruction streams, thereby offering slightly more flexibility than classical SIMD.
Each hardware element (PU) working on individual data item sometimes also referred as SIMD lane or channel. Modern <a href="/facts/Graphics_processing_unit/PTK1RQVp">graphics processing units</a> (GPUs) are often wide SIMD (typically >16 data lanes or channel) implementations. Some newer GPUs go beyond simple SIMD and integrate mixed-precision SIMD pipelines, which allow concurrent execution of 8-bit, 16-bit, and 32-bit operations in different lanes. This is critical for applications like AI inference, where mixed precision boosts throughput.
Additionally, SIMD can exist in both fixed and scalable vector forms. Fixed-width SIMD units operate on a constant number of data points per instruction, while scalable designs, like RISC-V Vector or ARM's SVE, allow the number of data elements to vary depending on the hardware implementation. This improves forward compatibility across generations of processors.

Single instruction, multiple data open-in-new

Single instruction, multiple data