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Hazard (computer architecture)
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<p>In the domain of <a href="/facts/Central_processing_unit/Jxp1bqMV">central processing unit</a> (CPU) <a href="/facts/CPU_design/HeNbj78g">design</a>, hazards are problems with the <a href="/facts/Instruction_pipeline/3zy6CcX1">instruction pipeline</a> in CPU <a href="/facts/Microarchitecture/NFRd4NUL">microarchitectures</a> when the next instruction cannot execute in the following clock cycle, and can potentially lead to incorrect computation results. Three common types of hazards are data hazards, structural hazards, and control hazards (branching hazards). </p><p>There are several methods used to deal with hazards, including <a href="/facts/Pipeline_stall/e3Ee0yJg">pipeline stalls</a>/pipeline bubbling, operand forwarding, and in the case of <a href="/facts/Out-of-order_execution/bM0dQM8m">out-of-order execution</a>, the <a href="/facts/Scoreboarding/oAz1Ws6q">scoreboarding</a> method and the <a href="/facts/Tomasulo_algorithm/Ro81atJm">Tomasulo algorithm</a>. </p>