Bus mastering

In <a href="/facts/Computing/Kghtm9fX">computing</a>, bus mastering is a feature supported by many <a href="/facts/Bus_(computing)/R45TKwS7">bus architectures</a> that enables a device connected to the bus to initiate <a href="/facts/Direct_memory_access/DWuVgclV">direct memory access</a> (DMA) transactions. It is also referred to as first-party DMA, in contrast with <a href="/facts/Third-party_DMA/DWuVgclV">third-party DMA</a> where a system <a href="/facts/DMA_controller/DWuVgclV">DMA controller</a> actually does the transfer.
Some types of buses allow only one device (typically the <a href="/facts/Central_processing_unit/Jxp1bqMV">CPU</a>, or its proxy) to initiate transactions. Most modern bus architectures, such as <a href="/facts/Peripheral_Component_Interconnect/n6CGuFvP">PCI</a>, allow multiple devices to bus master because it significantly improves performance for general-purpose <a href="/facts/Operating_system/8XTuvMh2">operating systems</a>. Some <a href="/facts/Real-time_operating_system/IvUCFwCL">real-time operating systems</a> prohibit peripherals from becoming bus masters, because the scheduler can no longer arbitrate for the bus and hence cannot provide deterministic latency.
While bus mastering theoretically allows one peripheral device to directly communicate with another, in practice almost all peripherals master the bus exclusively to perform DMA to <a href="/facts/Main_memory/wPHKFpdx">main memory</a>.
If multiple devices are able to master the bus, there needs to be a bus arbitration scheme to prevent multiple devices attempting to drive the bus simultaneously. A number of different schemes are used for this; for example <a href="/facts/SCSI/pxXulrBr">SCSI</a> has a fixed priority for each SCSI ID. PCI does not specify the algorithm to use, leaving it up to the implementation to set priorities.

Bus mastering open-in-new

Bus mastering