Transaction-level modeling

Transaction-level modeling (TLM) is an approach to modelling complex digital systems by using <a href="/facts/Electronic_design_automation/o4la3fmX">electronic design automation</a> software.: 1955  TLM is used primarily in the design and verification of complex <a href="/facts/System-on-a-chip/1RVvVe6N">systems-on-chip</a> (SoCs) and other electronic systems where traditional <a href="/facts/Register-transfer_level/SDA3ET30">register-transfer level</a> (RTL) modeling would be too slow or resource-intensive for system-level analysis. TLM language (TLML) is a <a href="/facts/Hardware_description_language/g19KvKCu">hardware description language</a>, usually, written in C++ and based on <a href="/facts/SystemC/SEqgs3ka">SystemC</a> library. TLMLs are used for modelling where details of communication among modules are separated from the details of the implementation of functional units or of the communication architecture. It's used for modelling of systems that involve complex data communication mechanisms.: 1955  The modeling approach focuses on the transactions or transfers of data between functional blocks rather than the detailed implementation of those blocks or their interconnections. This abstraction enables faster simulation speeds, often orders of magnitude faster than RTL, while maintaining sufficient accuracy for system-level design decisions, <a href="/facts/Software_development/UUfsAaYY">software development</a>, and architectural exploration.
Components such as buses or <a href="/facts/FIFO_(computing_and_electronics)/RctvBNgE">FIFOs</a> are modeled as channels, and are presented to modules using <a href="/facts/SystemC/SEqgs3ka">SystemC</a> interface classes. Transaction requests take place by calling interface functions of these channel models, which encapsulate low-level details of the information exchange. At the transaction level, the emphasis is more on the functionality of the data transfers – what data are transferred to and from what locations – and less on their actual implementation, that is, on the actual protocol used for data transfer. This approach makes it easier for the system-level designer to experiment, for example, with different bus architectures (all supporting a common abstract interface) without having to recode models that interact with any of the buses, provided these models interact with the bus through the common interface.
TLM is typically implemented using <a href="/facts/SystemC/SEqgs3ka">SystemC</a>, a <a href="/facts/C%252B%252B/Et0F2qn9">C++</a>-based modeling language and library developed specifically for system-level design. The <a href="/facts/Open_SystemC_Initiative/PtqWU00v">Open SystemC Initiative</a> (OSCI), now part of <a href="/facts/Accellera/PtqWU00v">Accellera</a>, has developed standardized TLM libraries that provide common interfaces and methodologies for transaction-level communication. However, the application of transaction-level modeling is not specific to the SystemC language and can be used with other languages. The concept of TLM first appears in the system-level language and modeling domain.
The methodology has become essential in modern <a href="/facts/Electronic_design_automation/o4la3fmX">electronic design automation</a> (EDA) flows, particularly for creating <a href="/facts/Virtual_platform/BLevU3sx">virtual platforms</a> that enable early <a href="/facts/Software_development/UUfsAaYY">software development</a> and system validation before hardware implementation is complete. TLM models serve as executable specifications that bridge the gap between high-level system requirements and detailed hardware implementations. TLMs are used for <a href="/facts/High-level_synthesis/fm5V1WN0">high-level synthesis</a> of <a href="/facts/Register-transfer_level/SDA3ET30">register-transfer level</a> (RTL) models for a lower-level modelling and implementation of system components. RTL is usually represented by a <a href="/facts/Hardware_description_language/g19KvKCu">hardware description language</a> source code (e.g. <a href="/facts/VHDL/H6Exdjfs">VHDL</a>, <a href="/facts/SystemC/SEqgs3ka">SystemC</a>, <a href="/facts/Verilog/efVqbKXg">Verilog</a>).: 1955–1957

Transaction-level modeling open-in-new

Transaction-level modeling