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Process–architecture–optimization model
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<p>Process–architecture–optimization is a development model for <a href="/facts/Central_processing_unit/Jxp1bqMV">central processing units</a> (CPUs) that <a href="/facts/Intel/SMF0gJJX">Intel</a> adopted in 2016. Under this three-phase (three-year) model, every <a href="/facts/Microprocessor/Fx9CaQht">microprocessor</a> <a href="/facts/Die_shrink/fgJ8nL4b">die shrink</a> is followed by a <a href="/facts/Microarchitecture/NFRd4NUL">microarchitecture</a> change and then by one or more optimizations. It replaced the two-phase (two-year) <a href="/facts/Tick%E2%80%93tock_model/CeKPeLur">tick–tock model</a> that Intel adopted in 2006. The tick–tock model was no longer economically sustainable, according to Intel, because production of ever smaller dies becomes ever more costly. </p>