Quad data rate

Quad data rate (QDR, or quad pumping) is a communication signaling technique wherein data are transmitted at four points in the clock cycle: on the rising and falling edges, and at two intermediate points between them. The intermediate points are defined by a second clock that is 90° out of <a href="/facts/Phase_(waves)/cpGtuVll">phase</a> from the first. The effect is to deliver four bits of data per signal line per clock cycle.
In a quad data rate system, the data lines operate at twice the frequency of the clock signal. This is in contrast to double data rate systems, in which the clock and data lines operate at the same frequency.
Quad data rate technology was introduced by <a href="/facts/Intel/SMF0gJJX">Intel</a> in its <a href="/facts/Pentium_4/6tIFuHIF">Willamette</a>-core <a href="/facts/Pentium_4/6tIFuHIF">Pentium 4</a> processor, and was subsequently employed in its <a href="/facts/Intel_Atom/1rB5zJyz">Atom</a>, Pentium 4, <a href="/facts/Celeron/kX00LpnM">Celeron</a>, <a href="/facts/Pentium_D/rLD9pQ8F">Pentium D</a> and <a href="/facts/Core_2/9gJP9o8p">Core 2</a> processor ranges. This technology has allowed Intel to produce chipsets and <a href="/facts/Central_processing_unit/Jxp1bqMV">processors</a> that can communicate with each other at data rates expected of the traditional <a href="/facts/Front-side_bus/LgYSB7Wl">front-side bus</a> (FSB) technology running from 400 <a href="/facts/Megatransfer/fgBCc5U9">MT</a>/s to 1600 MT/s, while maintaining a lower and thus more stable actual clock frequency of 100 MHz to 400 MHz.

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Quad data rate