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Single instruction, multiple threads
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<p>Single instruction, multiple threads (SIMT) is an execution model used in <a href="/facts/Parallel_computing/nQzcpzQt">parallel computing</a> where <a href="/facts/Single_instruction%2c_multiple_data/gQHWQSpo">single instruction, multiple data</a> (SIMD) is combined with <a href="/facts/Thread_(computing)/hh8WHyPd">multithreading</a>. It is different from <a href="/facts/SPMD/SEDIrB0l">SPMD</a> in that all instructions in all "threads" are executed in lock-step. The SIMT execution model has been implemented on several <a href="/facts/GPU/PTK1RQVp">GPUs</a> and is relevant for <a href="/facts/General-purpose_computing_on_graphics_processing_units/roBwsPY2">general-purpose computing on graphics processing units</a> (GPGPU), e.g. some <a href="/facts/Supercomputer/HT9NwGAN">supercomputers</a> combine CPUs with GPUs. </p><p>The processors, say a number p of them, seem to execute many more than p tasks. This is achieved by each processor having multiple "threads" (or "work-items" or "Sequence of SIMD Lane operations"), which execute in lock-step, and are analogous to <a href="/facts/SIMD_lanes/gQHWQSpo">SIMD lanes</a>. </p><p>The simplest way to understand SIMT is to imagine a multi-core system, where each core has its own register file, its own <a href="/facts/Arithmetic_logic_unit/SgIjPzSc">ALUs</a> (both SIMD and Scalar) and its own data cache, but that unlike a standard multi-core system which has multiple independent instruction caches and decoders, as well as multiple independent Program Counter registers, the instructions are synchronously broadcast to all SIMT cores from a single unit with a single instruction cache and a single instruction decoder which reads instructions using a single Program Counter. </p><p>The key difference between SIMT and <a href="/facts/SIMD_lanes/gQHWQSpo">SIMD lanes</a> is that each of the SIMT cores may have a completely different Stack Pointer (and thus perform computations on completely different data sets), whereas SIMD lanes are simply part of an ALU that knows nothing about memory per se. </p>