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Hardware verification language
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<p>A hardware verification language, or HVL, is a programming language used to verify the designs of <a href="/facts/Electronic_circuits/IRfQ6Cc2">electronic circuits</a> written in a <a href="/facts/Hardware_description_language/g19KvKCu">hardware description language</a>. HVLs typically include features of a <a href="/facts/High-level_programming_language/smjECUhx">high-level programming language</a> like <a href="/facts/C%252B%252B/Et0F2qn9">C++</a> or <a href="/facts/Java_/9ScgFyAL">Java</a> as well as features for easy bit-level manipulation similar to those found in <a href="/facts/Hardware_description_language/g19KvKCu">HDLs</a>. Many HVLs will provide constrained random stimulus generation, and functional coverage constructs to assist with complex hardware verification. </p><p><a href="/facts/SystemVerilog/wkBdc179">SystemVerilog</a>, OpenVera, <a href="/facts/E_(verification_language)/hRaWFL4S">e</a>, and <a href="/facts/SystemC/SEqgs3ka">SystemC</a> are the most commonly used HVLs. <a href="/facts/SystemVerilog/wkBdc179">SystemVerilog</a> attempts to combine HDL and HVL constructs into a single standard. </p>