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Instruction set simulator
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<p>An instruction set simulator (ISS) is a <a href="/facts/Simulation/Q4QJV1oI">simulation</a> <a href="/facts/Model_(abstract)/hgysE2kP">model</a>, usually coded in a <a href="/facts/High-level_programming_language/smjECUhx">high-level programming language</a>, which mimics the behavior of a mainframe or <a href="/facts/Microprocessor/Fx9CaQht">microprocessor</a> by "reading" instructions and maintaining internal variables which represent the processor's <a href="/facts/Processor_register/32RvbUdz">registers</a>. </p><p>Instruction simulation is a methodology employed for one of several possible reasons: </p> <ul><li>To simulate the <a href="/facts/Instruction_set_architecture/8p8vwUeE">instruction set architecture</a> (ISA) of a future processor to allow software development and test to proceed without waiting for the development and production of the hardware to finish. This is often known as "shift-left" or "pre-silicon support" in the hardware development field. A <a href="/facts/Full_system_simulator/JTqrTTCj">full system simulator</a> or <a href="/facts/Virtual_platform/BLevU3sx">virtual platform</a> for the future hardware typically includes one or more instruction set simulators.</li> <li>To simulate the <a href="/facts/Machine_code/bgdQ1Fxf">machine code</a> of another hardware device or entire computer for upward <a href="/facts/Compatibility_mode_(software)/lsVy9cKG">compatibility</a>.</li></ul> For example, the <a href="/facts/IBM_1401/SrdHgTWx">IBM 1401</a> was simulated on the later <a href="/facts/IBM%2f360/7znvpy4K">IBM/360</a> through use of <a href="/facts/Microcode/XQEsr2X3">microcode</a> <a href="/facts/Emulator/FMHE8qDj">emulation</a>. <ul><li>To monitor and execute the machine code instructions (but treated as an input stream) on the same hardware for test and debugging purposes, e.g. with <a href="/facts/Memory_protection/3zDwN2SG">memory protection</a> (which protects against accidental or deliberate <a href="/facts/Buffer_overflow/uMFduL4B">buffer overflow</a>).</li> <li>To improve the speed performance—compared to a slower <a href="/facts/Cycle-accurate_simulator/JTqrTTCj">cycle-accurate simulator</a>—of simulations involving a processor core where the processor itself is not one of the elements being verified; in <a href="/facts/Hardware_description_language/g19KvKCu">hardware description language</a> design using <a href="/facts/Verilog/efVqbKXg">Verilog</a> where simulation with tools like ISS can be run faster by means of "<a href="/facts/Verilog/efVqbKXg">PLI</a>" (not to be confused with <a href="/facts/PL%2f1/469mVYgd">PL/1</a>, which is a <a href="/facts/Programming_language/cWTYbgWa">programming language</a>).</li></ul>