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Load–store architecture
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<p>In <a href="/facts/Computer_engineering/5x1TRKGo">computer engineering</a>, a load–store architecture (or a register–register architecture) is an <a href="/facts/Instruction_set_architecture/8p8vwUeE">instruction set architecture</a> that divides instructions into two categories: <a href="/facts/Memory_(computing)/hQKVQ51J">memory</a> access (<a href="/facts/Load_and_store/8QEBxzRl">load and store</a> between memory and <a href="/facts/Processor_register/32RvbUdz">registers</a>) and <a href="/facts/Arithmetic_logic_unit/SgIjPzSc">ALU</a> operations (which only occur between registers).: 9–12 </p><p>Some <a href="/facts/Reduced_instruction_set_computing/aQbGM62p">RISC</a> architectures such as <a href="/facts/PowerPC/DqmM9y50">PowerPC</a>, <a href="/facts/SPARC/m7KhEtET">SPARC</a>, <a href="/facts/RISC-V/pUSKDat1">RISC-V</a>, <a href="/facts/ARM_architecture/SALsYA79">ARM</a>, and <a href="/facts/MIPS_architecture/efV4KgK4">MIPS</a> are load–store architectures.: 9–12 </p><p>For instance, in a load–store approach both operands and destination for an ADD operation must be in registers. This differs from a <a href="/facts/Register%25E2%2580%2593memory_architecture/w9fXBcrx">register–memory architecture</a> (for example, a <a href="/facts/Complex_instruction_set_computing/Ucvyh2xq">CISC</a> instruction set architecture such as <a href="/facts/X86/Kypq5fgu">x86</a>) in which one of the operands for the ADD operation may be in memory, while the other is in a register.: 9–12 </p><p>The earliest example of a load–store architecture was the <a href="/facts/CDC_6600/QpnT1Ltl">CDC 6600</a>.: 54–56 Almost all <a href="/facts/Vector_processor/nYAsIKT0">vector processors</a> (including many <a href="/facts/GPUs/PTK1RQVp">GPUs</a>[<i>better source needed</i>]) use the load–store approach. </p>