Clock gating

<p>In <a href="/facts/Computer_architecture/tHtwxgR2">computer architecture</a>, clock gating is a popular <a href="/facts/Power_management/fWv2k2sP">power management</a> technique used in many <a href="/facts/Synchronous_circuit/k3yddBIN">synchronous circuits</a> for reducing dynamic <a href="/facts/Power_dissipation/C134STy1">power dissipation</a>, by removing the <a href="/facts/Clock_signal/9UfTzGHx">clock signal</a> when the circuit, or a subpart of it, is not in use or ignores the clock signal. Clock gating <a href="/facts/Energy_conservation/Sk7d6Dg2">saves power</a> by pruning the <a href="/facts/Clock_signal/9UfTzGHx">clock tree</a>, at the cost of adding more logic to a circuit. Pruning the clock disables portions of the circuitry so that the <a href="/facts/Flip-flop_(electronics)/vA99xjM7">flip-flops</a> in them do not switch state, as switching the state consumes power. When not being switched, the <a href="/facts/Switching_power/BNbaFmEL">switching power</a> consumption goes to zero, and only <a href="/facts/Leakage_(semiconductors)/Nd6PNxhV">leakage currents</a> are incurred. This technique is particularly effective in systems with significant idle time or predictable periods of inactivity within specific modules.<a href="https://anysilicon.com/the-ultimate-guide-to-clock-gating/">[1]</a>
</p><p>Although <a href="/facts/Asynchronous_circuit/n4ah2j7H">asynchronous circuits</a> by definition do not have a global "clock", the term perfect clock gating is used to illustrate how various clock gating techniques are simply approximations of the data-dependent behavior exhibited by asynchronous circuitry. As the <a href="/facts/Granularity_(parallel_computing)/3UJW0Iu6">granularity</a> on which one gates the clock of a synchronous circuit approaches zero, the power consumption of that circuit approaches that of an asynchronous circuit: the circuit only generates logic transitions when it is actively computing.
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Clock gating open-in-new

Clock gating