Electronic system-level design and verification

Electronic system level (ESL) design and verification is an electronic design methodology, focused on higher abstraction level concerns. The term Electronic System Level or ESL Design was first defined by <a href="/facts/Gartner/9hd9zakC">Gartner Dataquest</a>, an EDA-industry-analysis firm, on February 1, 2001. It is defined in ESL Design and Verification as: "the utilization of appropriate abstractions in order to increase comprehension about a system, and to enhance the probability of a successful implementation of functionality in a cost-effective manner."
The basic premise is to model the behavior of the entire system using a low-level language such as <a href="/facts/C_(programming_language)/Ky2No763">C</a>, <a href="/facts/C%2B%2B/Et0F2qn9">C++</a>, or using graphical "model-based" design tools. Newer languages are emerging that enable the creation of a model at a higher level of abstraction including general purpose system design languages like <a href="/facts/SysML/66N9ASg1">SysML</a> as well as those that are specific to embedded system design like SMDL and SSDL. Rapid and correct-by-construction implementation of the system can be automated using <a href="/facts/Electronic_design_automation/o4la3fmX">EDA</a> tools such as <a href="/facts/High-level_synthesis/fm5V1WN0">high-level synthesis</a> and <a href="/facts/Embedded_software/zY8EeYCJ">embedded software</a> tools, although much of it is performed manually today. ESL can also be accomplished through the use of <a href="/facts/SystemC/SEqgs3ka">SystemC</a> as an abstract <a href="/facts/Modeling_language/9Nm6YLcR">modeling language</a>.
ESL is an established approach at many of the world’s leading <a href="/facts/System-on-a-chip/1RVvVe6N">System-on-a-chip</a> (SoC) design companies, and is being used increasingly in <a href="/facts/System_design/hFWYoaNP">system design</a>. From its genesis as an <a href="/facts/Algorithm/fnl5NmRt">algorithm</a> <a href="/facts/Computer_model/Re6o8vzN">modeling</a> methodology with 'no links to implementation', ESL is evolving into a set of complementary methodologies that enable embedded system design, verification, and <a href="/facts/Debugging/QtdpPJT0">debugging</a> through to the <a href="/facts/Computer_hardware/8jSjsCNv">hardware</a> and <a href="/facts/Computer_software/RP79lVSW">software</a> implementation of custom <a href="/facts/System-on-a-chip/1RVvVe6N">SoC</a>, system-on-<a href="/facts/FPGA/M8LSGcAU">FPGA</a>, system-on board, and entire multi-board systems.
Design and verification are two distinct disciplines within this methodology. Some practices are to keep the two elements separate, while others advocate for closer integration between design and verification.

Electronic system-level design and verification open-in-new

Electronic system-level design and verification