Re-order buffer

A re-order buffer (ROB) is a hardware unit used in an extension to <a href="/facts/Tomasulo%2527s_algorithm/Ro81atJm">Tomasulo's algorithm</a> to support <a href="/facts/Out-of-order_execution/bM0dQM8m">out-of-order</a> and <a href="/facts/Speculative_execution/AkA84o5n">speculative</a> instruction execution. The extension forces instructions to be committed in-order.
The buffer is a <a href="/facts/Circular_buffer/Xu7vpzmP">circular buffer</a> (to provide a <a href="/facts/FIFO_(computing_and_electronics)/RctvBNgE">FIFO</a> instruction ordering queue) implemented as an <a href="/facts/Array_(data_structure)/BKGvF8AM">array/vector</a> (which allows recording of results against instructions as they complete out of order).
There are three stages to the Tomasulo algorithm: "Issue", "Execute", "Write Result". In an extension to the algorithm, there is an additional "Commit" stage. During the Commit stage, instruction results are stored in a register or memory. The "Write Result" stage is modified to place results in the re-order buffer. Each instruction is tagged in the <a href="/facts/Reservation_station/K30jCKs0">reservation station</a> with its index in the ROB for this purpose.
The contents of the buffer are used for data dependencies of other instructions scheduled in the buffer. The head of the buffer will be committed once its result is valid. Its dependencies will have already been calculated and committed since they must be ahead of the instruction in the buffer though not necessarily adjacent to it. Data dependencies between instructions would normally stall the pipeline while an instruction waits for its dependent values. The ROB allows the pipeline to continue to process other instructions while ensuring results are committed in order to prevent <a href="/facts/Data_hazard/hXItYfk1">data hazards</a> such as read ahead of write (RAW), write ahead of read (WAR) and write ahead of write (WAW). 
There are additional fields in every entry of the buffer to support the extended algorithm:

<ul><li>Instruction type (jump, store to memory, store to register)</li>
<li>Destination (either memory address or register number)</li>
<li>Result (value that goes to destination or indication of a (un)successful jump)</li>
<li>Validity (does the result already exist?)</li></ul>
The consequences of the re-order buffer include precise <a href="/facts/Exception_handling/VrJxgb9r">exceptions</a> and easy <a href="/facts/Rollback_(data_management)/HNtToVYw">rollback</a> control of <a href="/facts/Branch_target_predictor/ImoX6k7L">target address mis-predictions</a> (branch or jump). When jump prediction is not correct or a nonrecoverable exception is encountered in the instruction stream, the ROB is cleared of all instructions (by setting the circular queue tail to the head) and reservation stations are re-initialized.

Re-order buffer open-in-new

Re-order buffer