Bus functional model

A bus functional model (BFM), also known as a transaction verification model (TVM) is a non-<a href="/facts/Logic_synthesis/w35wWFfK">synthesizable</a> software model of an <a href="/facts/Integrated_circuit/fjn6vg7C">integrated circuit</a> component having one or more external buses. The emphasis of the model is on simulating system bus transactions prior to building and testing the actual hardware. BFMs are usually defined as tasks in <a href="/facts/Hardware_description_language/g19KvKCu">Hardware description languages</a> (HDLs), which apply stimuli to the design under verification via complex waveforms and protocols. A BFM is typically implemented using hardware description languages such as <a href="/facts/Verilog/efVqbKXg">Verilog</a>, <a href="/facts/VHDL/H6Exdjfs">VHDL</a>, <a href="/facts/SystemC/SEqgs3ka">SystemC</a>, or <a href="/facts/SystemVerilog/wkBdc179">SystemVerilog</a>.
Typically, BFMs offer a two-sided interface: One interface side drives and samples low-level signals according to the bus protocol. On its other side, tasks are available to create and respond to bus transactions. BFMs are often used as reusable building blocks to create simulation test benches, in which the bus interface ports of a design under test are connected to appropriate BFMs.
Another common application of BFMs is the provision of substitute models for <a href="/facts/Intellectual_Property/PqHW9mVP">IP</a> components: Instead of a netlist or RTL design of an IP component, a 3rd party IP supplier might provide only a BFM suitable for verification purposes. The actual IP component in the form of a <a href="/facts/Netlist/Wwt4M3jo">gate-level netlist</a> can be directly provided to the foundry by the IP provider. 
In the past, BFM were treated as a non-synthesizable entity, however recently BFMs are becoming available as synthesizable models as well.

Bus functional model open-in-new

Bus functional model