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MyHDL
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<p>MyHDL is a <a href="/facts/Python_/YbuGqofa">Python</a>-based <a href="/facts/Hardware_description_language/g19KvKCu">hardware description language</a> (HDL). </p><p>Features of MyHDL include: </p> <ul><li>The ability to generate <a href="/facts/VHDL/H6Exdjfs">VHDL</a> and <a href="/facts/Verilog/efVqbKXg">Verilog</a> code from a MyHDL design.</li> <li>The ability to generate a testbench (Conversion of test benches) with test vectors in VHDL or Verilog, based on complex computations in Python.</li> <li>The ability to convert a list of signals.</li> <li>The ability to convert output verification.</li> <li>The ability to do co-simulation with Verilog.</li> <li>An advanced datatype system, independent of traditional datatypes. MyHDL's translator tool automatically writes conversion functions when the target language requires them.</li></ul> <p>MyHDL is developed by Jan Decaluwe. </p>